Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-12-05
2004-09-28
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S700000, C438S725000, C438S745000
Reexamination Certificate
active
06797627
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of removing polymer from a surface that has been etched as part of creating a damascene structure.
(2) Description of the Prior Art
One of the more important aspects of fabricating very and ultra large scale integration (VLSI and ULSI) semiconductor devices is the fabrication of metal interconnect lines and vias that provide the interconnection of integrated circuits in semiconductor devices. The invention specifically addresses interconnect aspects as they relate to the creation of dual damascene structures. For the creation of a dual damascene structure, an insulating layer or a dielectric layer, such as silicon oxide, is patterned with trenches for conductive lines and openings for vias. The openings and trenches are simultaneously filled with a metal, such as aluminum, and serve to interconnect active and/or passive elements of an integrated circuit. The dual damascene process is also used for forming multilevel conductive lines of metal, such as copper, in insulating layers, such as polyimide, of multilayer substrates on which semiconductor devices are mounted.
Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings also are formed.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating processing steps. The dual damascene process requires two masking steps to form first the via pattern after which the pattern for the conductive lines is formed.
For the dual damascene process, the processing steps can follow three approaches, as follows:
Approach 1, the via is created first. The vias are formed by resist patterning after which an etch through a triple layer dielectric stack is performed. This is followed by patterning the conductor in the top layer of SiO
2
thereby using a layer of SiN as an etch stop layer.
Approach 2, the conductor first process. The conductor pattern is formed by resist patterning and by etching the conductor pattern into an upper dielectric layer, using an SiN layer that is deposited between two layers of dielectric as an etch stop layer. This is followed by via resist patterning and etching through the thin layer of SiN and a lower dielectric layer.
Approach 3, the etch stop layer first. The first SiO
2
layer is deposited, followed by the thin layer of SiN as etch stop, followed by the via resist patterning and etching of the SiN layer. This is followed by depositing the top SiO
2
layer and then the conductor patterning. In etching the conductor pattern in the top SiO
2
layer, the etching process will be stopped by the SiN layer except where the via holes are already opened in the SiN layer thereby completing the via holes etching in the first SiO
2
layer simultaneously.
Etch stop layers are frequently used during the process of creating dual damascene structures. The art is aggressively moving toward semiconductor devices with sub-micron and deep sub-micron device features. For these devices, the creation of via holes and the effect that the deposits of polymers has on the performance of via plugs become critical issues. An etch stop layer must typically be removed from the bottom of a via hole in order to contact the underlying layer of metal. Remnants of polymers typically have a severely negative effect on resistive contact performance of via plugs and must therefore be removed as part of the process of creating via plugs. The invention provides a method that effectively removes such polymers. This is a requirement for the creation of devices with deep sub-micron dimensions, which comprises the creation of via holes with a 0.13 &mgr;m diameter.
U.S. Pat. No. 6,265,320 BI (Shi et al.) shows a H
2
plasma post treatment and low k process.
U.S. Pat. No. 5,660,682 (Zhao et al.) shows a H
2
plasma post clean.
U.S. Pat. No. 6,204,192 BI (Zhao et al.) shows a plasma clean process.
U.S. Pat. No. 5,882,489 (Bersin et al.), U.S. Pat. No. 5,567,271 (Chu et al.), U.S. Pat. No. 6,248,665 BI (Bao et al.) and U.S. Pat. No. 6,037,664 (Zhao et al.) are related processes.
SUMMARY OF THE INVENTION
A principle objective of the invention is to remove polymers, possibly mixed with copper oxide residue, from semiconductor surfaces.
Another objective of the invention is to enable the removal of polymers, possibly mixed with copper oxide residue, without detrimental effects on exposed semiconductor surfaces.
Yet another objective of the invention is to improve resistive performance of via plugs by removing contact inhibiting materials from surfaces over which contact plugs are formed.
A still further objective of the invention is to optimize the creation of contact plugs for devices having deep sub-micron device dimensions.
In accordance with the objectives of the invention a new method is provided for the removal of polymers, possibly mixed with copper oxide residue, from exposed surfaces after an etch stop layer has been removed. The exposed surfaces are treated with a first plasma etch followed by a DI water rinse after which a second plasma etch of the exposed surfaces is performed. By selecting the chemistry and the conditions for the first and the second plasma etch, polymer residues and formed copper oxide residues are removed from the exposed surfaces.
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patent: 6153530 (2000-11-01), Ye et al.
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patent: 6248665 (2001-06-01), Bao et al.
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Chiao Li-Chie
Lin Li-Te S.
Shih Hsin-Ching
Su Yi-Nien
Chen Kin-Chan
Haynes and Boone LLP
Taiwan Semiconductor Manufacturing Company , Ltd.
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