Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-12-04
2001-07-17
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S669000, C438S720000, C438S742000
Reexamination Certificate
active
06261934
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and specifically to methods for etching semiconductor-free transistor gate stacks.
BACKGROUND: THE NEED FOR LOW-RESISTIVITY GATE MATERIALS
One of the major problems in shrinking integrated circuit geometries is the distributed resistance and parasitic capacitance of the signal lines, which reduce the propagation speed of signals. The additional delays thus introduced reduce the potential speed of the chip.
This is a particular problem for DRAMs, since the wordlines are densely packed together, and the capacitive coupling between adjacent lines becomes very significant. Moreover, the sheet resistance of the lines cannot usefully be improved by increasing the height of the lines, since this also increases the capacitive coupling between adjacent lines. There has therefore been great pressure to find materials with a lower resistivity to replace the traditional polysilicon/silicide lines. This has impelled efforts to design metal into the gate line structure. One example of this is a gate stack structure which includes a metal over a conductive nitride over the gate dielectric, without any semiconductor material in the stack.
BACKGROUND: THE PROBLEM OF BURIED CHANNELS
It has long been recognized that the use of an N-type polysilicon gate for P-channel transistors will tend to produce a buried channel for submicron transistor geometries. This is due to the difference in work-function between the channel and the gate. The “work-function” of a material is the energy difference between that material and vacuum, for a single carrier (e.g. a single electron).
As geometries shrink into the deep submicron regime (below 0.5 or 0.35 micron), such buried channels become very undesirable (due e.g. to reduced drive capability). Thus one of the constraints on new gate materials is a good work-function match to the semiconductor used.
BACKGROUND: METAL GATE STRUCTURES
The fabrication of advanced sub-tenth-micron devices will require replacement of the highly doped polysilicon gate electrode by new gate materials. The gate electrode stack for advanced devices should provide low sheet resistance to minimize interconnect delays, have a work function near to the silicon mid-gap to enable both n and p-type transistors to operate in surface channel mode, and prevent gate electrode depletion effects (to assure that the effective oxide thickness is equal to the physical oxide thickness).
Titanium nitride is a very promising candidate for gate electrode material. It has a work function near the mid-gap point of silicon (4.65 eV) and eliminates gate depletion effects. However, titanium nitride has a quite high resistivity (120 m&OHgr;-cm), and therefore needs to be used in conjunction with a material with higher conductivity for low interconnect delays to be achieved. For that purpose, tungsten (resistivity of 8 m&OHgr;-cm) has been used.
The definition of the gate electrode stack on ultra-thin (<3 nm) gate oxides for sub-tenth-micron transistors imposes a severe challenge to the etch process. Very high selectivity to SiO2 has to be achieved to avoid oxide punchthrough and subsequent damage to the silicon in the source and drain regions. Even when successfully stopped in the gate oxide, the conventional gate etch process introduces corner damage to the gate structure that needs to be annealed to guarantee good gate oxide integrity (GOI) properties of the transistor. However, it is difficult to anneal the corner damage on metal gate structures, since tungsten and titanium nitride readily oxidize in conventional oxidation processes. One solution to this problem might be to use a wet etch to slightly undercut the titanium nitride layer, moving the active gate region away from the damaged corners. However, since the selectivity of the wet etch towards tungsten is very low, the tungsten sidewall needs to be protected with a spacer prior to the titanium nitride undercut etch. This adds significant complexity to the device fabrication flow and severely reduces the process window, since the amount of undercut, and consequently the effective gate length, depends on the spacer thickness. Another approach might be to etch the titanium nitride with a process that does not cause corner damage.
Chlorine-based plasma etching chemistries are commonly used for etching titanium nitride. However, in a W/TiN/SiO2 structure, chlorine-based titanium nitride etch chemistries can cause corrosion of the tungsten layer.
Metal+Barrier+Dielectric Gate Stack Process and Structure
The present application discloses new processes for fabricating metal-on-conductive-diffusion-barrier-on-gate-dielectricstructures. This is done by: etching the metal, by plasma-assisted anisotropic etching, down to and into the barrier layer; and then etching the remainder of the barrier layer by a dry chemical-downstream-etching process, during which the barrier layer is not exposed to ion bombardment. In one specific example, a chemical downflow etch based on a chemistry consisting of oxygen (O2) and hexafluoroethane (C2F6) was used to successfully fabricate sub-tenth-micron W/TiN gate structures on ultra-thin (<3 nm) silicon dioxide. The electrical characteristics of the devices indicated excellent process uniformity and no charge or corner damage effects. In some but not all embodiments, a photoresist ashing step was performed after the plasma-assisted metal etch, but before the final barrier layer etch.
Advantages of the disclosed methods and structures include:
Controllable titanium nitride etch rate and undercut;
All dry etch and clean process;
Sub-tenth-micron gate lengths attainable;
Damage free gate oxides at and below 3 nm thickness are attainable;
Better control of titanium nitride undercut with dry process;
Ability to etch metal gate without damaging underlying gate oxide;
Ability to etch sub-tenth-micron metal gates;
Resist and titanium nitride removed in a single step;
No smile oxidation is required since the gate oxide is undamaged;
An aggressive tungsten etch, with heavy bombardment, can be used;
Plasma damage to the gate oxide is avoided; and
The problem of wet chemical disposal is eliminated.
Moreover, no tungsten corrosion occurs as a result of the brief TiN fluoro-etch times used in the presently preferred embodiment.
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Kraft Robert
Rotondaro Antonio L. P.
Brady III Wade James
Fourson George
Garcia Joannie Adelle
Stewart Alan K.
Telecky , Jr. Frederick J.
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