Driving circuitry for EEPROM memory cell

Details Driving circuitry for EEPROM memory cell Driving circuitry for EEPROM memory cell

1988-09-02

1989-04-18

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365185, 365218, G11C 1184, G11C 700

Patent

active

048233188

ABSTRACT:
A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising four P-channel transistors and two N-channel transistors as well as four switches. The circuit comprises a two-transistor inverter with a feedback transistor and three isolating transistors that prevent excessive currents and voltages from damaging internal and external circuit components.

REFERENCES:
patent: 4720816 (1988-01-01), Matsuoka et al.
patent: 4761764 (1988-08-01), Watanabe

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