Driving circuit for a shared sense amplifier with increased spee

Details Driving circuit for a shared sense amplifier with increased spee Driving circuit for a shared sense amplifier with increased spee

1985-08-16

1988-01-12

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365233, 365207, 307482, G11C 700, G11C 800, G11C 702

Patent

active

047195975

ABSTRACT:
A cut-off clock .phi..sub.5 generated by a cut-off clock generation circuit PG is supplied to a decode circuit DEC. The decode circuit DEC decodes the cut-off clock .phi..sub.5 to produce two types of cut-off clocks .phi..sub.5L and .phi..sub.5R. The two types of cut-off clocks .phi..sub.5L and .phi..sub.5R are supplied to a control clock generation circuit as shown in FIG. 3 or 11, which in turn produces control clocks .phi..sub.2L and .phi..sub.2R. The control clocks .phi..sub.2L and .phi..sub.2R are supplied to a shared sense amplifier of FIG. 1, to control on-off operations of transfer transistors 7.sub.L, 8.sub.L, 7.sub.R and 8.sub.R.

REFERENCES:
patent: 4606010 (1986-08-01), Saito
Smith et al., IEEE Journal of Solid-State Circuits, vol. SC-15, No. 2, Apr. 1980, pp. 184-189.
Barnes et al., IEEE Journal of Solid-State Circuits, vol. SC-15, No. 5, Oct. 1980, pp. 831-839.

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