Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1996-10-29
1998-09-22
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
326 58, 326 83, G11C 700, H03K 1900
Patent
active
058124616
ABSTRACT:
The invention is an improved bank select read only memory in which the bit lines and virtual ground lines are precharged to ground instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines are selected for the selected bit and both selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines in the memory array are precharged to ground during the precharge phase. Next, during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line at ground and switch the second virtual ground line to a positive voltage. All bit lines are precharged to ground during the precharge phase. In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage. If the selected memory core FET is programmed with a high threshold voltage, the bit line remains floating at the ground level, or it may be held at ground by means of the second virtual ground line, which is held at ground, and by low threshold core FETs, adjacent to the selected core FET, which are connected to the selected word line. The total diffusion capacitance on a virtual ground line is minimized when the memory cells connected to the line are programmed with more logic zeros than logic ones.
REFERENCES:
patent: 5146111 (1992-09-01), Ciraula
patent: 5165046 (1992-11-01), Hesson
patent: 5436577 (1995-07-01), Lee
Amneus Robert D.
Komarek James A.
Padgett Clarence W.
Tanner Scott B.
Creative Integrated Systems, Inc.
Dawes Daniel L.
Mai Son
Nelms David C.
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