DRAM with vertical transistor and trench capacitor memory...

Details DRAM with vertical transistor and trench capacitor memory... DRAM with vertical transistor and trench capacitor memory...

2005-02-01

2005-02-01

Thomas, Tom (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S242000, C438S246000, C438S389000, C438S392000

Reexamination Certificate

active

06849496

ABSTRACT:
A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.

REFERENCES:
patent: 5119153 (1992-06-01), Korman et al.
patent: 5225697 (1993-07-01), Malhi et al.
patent: 6153902 (2000-11-01), Furukawa et al.
patent: 6204140 (2001-03-01), Gruening et al.
patent: 6281539 (2001-08-01), Mandelman et al.
patent: 6284593 (2001-09-01), Mandelman et al.
patent: 6333533 (2001-12-01), Furukawa et al.
Article entitled A Novel Trench DRAM Cell with a VERTICAL Access Transistor AndBuriEdSTrap (VERI BEST) for 4 Gb/16Gb by U. Gruening et al., IEDM (IEEE), 1999.

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