DRAM structure with multiple memory cells sharing the same bit-l

Details DRAM structure with multiple memory cells sharing the same bit-l DRAM structure with multiple memory cells sharing the same bit-l

1998-10-01

2000-05-02

Elms, Richard T.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438238, 257296, H10L 218242

Patent

active

06057187&

ABSTRACT:
The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact. The DRAM structure of the present invention comprises: a substrate; an active region formed on the substrate, with a center region and a plurality of protrusion regions connecting to the two sides of the center region; a plurality of word-lines, disconnected from each other, each crossing the corresponding protrusion region; a plurality of channel regions, formed where the protrusion region overlaps with the word-lines; a plurality of source regions, formed at the outer areas of the channel regions; a sharing drain region, formed at the center region of the active region; a bit-line contact, formed on surface of the sharing drain region; a bit-line, crossing the center region and electrically connected to the sharing drain region via the bit-line contact; a plurality of capacitors, electrically connected to the source regions; and a plurality of metal lines, electrically connected to the corresponding word-lines.

REFERENCES:
patent: 5374576 (1994-12-01), Kimura et al.
patent: 5583358 (1996-12-01), Kimura et al.
patent: 5828094 (1998-10-01), Lee
Method of Fabricating a New Merged Stacked Trench Capacitor Memory Cell Structure, IBM Technical Disclosure Bulletin, Dec. 1991, pp. 472-476.

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