DRAM sensing scheme and isolation circuit

Details DRAM sensing scheme and isolation circuit DRAM sensing scheme and isolation circuit

1998-03-30

2000-01-18

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Precharge

365149, 365202, 365207, G11C 700

Patent

active

060162791

ABSTRACT:
A pre-charge and isolation circuit for a folded bit line DRAM array to reduce noise coupling between adjacent bit lines of a DRAM array by allowing only one bit line to be connected to a sense amplifier, while the complementary bit line remains at a reference voltage level is disclosed. The isolation pre-charge circuit will be connected to a pair of bit lines within a DRAM array to pre-charge portions the pair of bit lines to a reference voltage level and to connect a selected DRAM cell to a latching sense amplifier.

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Bellaouar et al. "Low Power Digital VLSI Design-Circuits and Systems" Kiuwer Academic, Ch. 6, sec 6.2.13.1, p. 381-3, 1995.
Aoki et al. "A 60ns 16mb CMOS DRAM With a Transposed Data-Line Structure" IEEE Trans. Solid-State Circuits, SC-23, No. 5, p.1113, 1988.

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