DRAM process with a multilayer stack structure

Details DRAM process with a multilayer stack structure DRAM process with a multilayer stack structure

1997-11-21

1999-10-12

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438970, H01L 218242

Patent

active

059666005

ABSTRACT:
A DRAM is formed using a process which uses few critical lithography steps and which provides capacitor electrodes and bit line contacts in a self-aligned manner in a common set of processing steps. A multilayer stack including a gate oxide layer, a gate electrode layer, an etch stop layer, and a thicker sacrificial layer are provided over the active device regions of a semiconductor substrate. Photolithography and etching define gate electrodes and wiring lines with patterned etch stop layers and patterned sacrificial layers over and self-aligned with the gate electrodes and wiring lines. Source/drain regions are formed self aligned to the patterned stacks and then an insulating spacer is provided alongside the edges of the gate electrodes. A relatively thin, conformal polysilicon layer is provided over the patterned stacks and in contact with the source/drain regions adjacent the gate electrodes. A planarizing layer is provided to fill in the gaps over the polysilicon layer between the stacks of gate electrodes, patterned etch stop layers and patterned sacrificial layers. A polishing process is performed to remove the conductive layer over the patterned sacrificial layers. The exposed sacrificial layer and the planarizing layers are removed to provide lower capacitor electrodes with vertically extending fins and bit line contacts with landing pads that facilitate making contacts to the bit line contacts. Processing continues to provide a capacitor dielectric layer, an upper capacitor electrode and a bit line contact to complete the DRAM.

REFERENCES:
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5362666 (1994-11-01), Dennison
patent: 5488011 (1996-01-01), Figura et al.

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