DRAM partial refresh circuits and methods

Details DRAM partial refresh circuits and methods DRAM partial refresh circuits and methods

2006-01-03

2006-01-03

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030, C365S230060

Reexamination Certificate

active

06982917

ABSTRACT:
Circuits and methods for refreshing memory banks in a DRAM are provided. A refresh circuit is provided in a DRAM having at least one memory bank and a plurality of word lines connected to memory locations in the memory bank. The word lines are subdivided into first and second groups of subword lines. The refresh circuit includes a delay circuit, a first driving circuit, and a second driving circuit. The delay circuit receives a refresh signal and outputs a delayed refresh signal a predetermined time delay later. The first driving circuit responds to the refresh signal by driving word lines in the first group of subword lines and the second driving circuit responds to the delayed refresh signal by driving word lines in the second group of subword lines.

REFERENCES:
patent: 5835436 (1998-11-01), Ooishi
patent: 6449204 (2002-09-01), Arimoto et al.
patent: 6590822 (2003-07-01), Hwang et al.
patent: 1020000009468 (2000-02-01), None
patent: 1002696180000 (2000-07-01), None
Notice to Submit Response—issued by Korean Patent Office, Aug. 29, 2003.

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