DRAM memory and method for fabricating a DRAM memory cell

Details DRAM memory and method for fabricating a DRAM memory cell DRAM memory and method for fabricating a DRAM memory cell

2005-02-10

2008-11-04

Pham, Thanhha (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C257SE21646

Reexamination Certificate

active

07445985

ABSTRACT:
A DRAM memory cell arrangement having memory cells each having a trench capacitor and a fin field-effect transistor or FinFET for addressing the trench capacitor. The memory cells are arranged in cell rows which are offset with respect to one another and are separated from one another by trench insulator structures. Word lines orthogonal to the cell rows mesh in comblike fashion between the cell rows and alternately traverse trench capacitors and channel regions of fin field-effect transistors. By means of a on-photolithographic mask having mask sections aligned with the trench capacitors, trench-insulator structures are provided in each case between a sidewall gate section of a word line and the adjoining trench capacitor, said trench-insulator structures decoupling the respective trench capacitor from the traversing word line.

REFERENCES:
patent: 2006/0056228 (2006-03-01), Schloesser et al.

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