DRAM having self-timed burst refresh mode

Details DRAM having self-timed burst refresh mode DRAM having self-timed burst refresh mode

1993-10-12

1995-07-04

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

365236, 365203, G11C 11401, G11C 11406

Patent

active

054306809

ABSTRACT:
Burst refresh mode circuitry is provided for a memory having cells in rows and columns, sense amplifiers and Latch N/Latch P driver circuitry, a RAS buffer, refresh counters, address buffers, row decoders, precharge circuitry producing shorting clocks, and a refresh detector circuit coupled to the Latch P circuitry to provide a restore finished (RF) signal indicative that a refresh cycle is substantially completed. Burst refresh mode entry circuitry detects proper conditions for entering burst refresh mode. An auto-refresh burst refresh mode circuit causes the RAS buffer to generate a new internal RAS signal. Burst refresh mode logic has counters to count the number of rows that have been refreshed. The system self-times the refreshing by responding to the restore finished signal. A delay circuit interposes a short delay for the precharge before another row is automatically refreshed in the burst refresh mode. Battery back-up mode circuitry is partially disabled.

REFERENCES:
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patent: 4984209 (1991-01-01), Rajaram et al.
patent: 5305274 (1994-04-01), Proebsting
Konishi et al., "A 38 ns 4 Mb DRAM with a Battery Back-up (BBU) Mode", 1990 IEEE International Solid-State Circuits Conference pp. 230-231, 303 (Feb. 16, 1990).

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