DRAM having offset vertical transistors and method

Details DRAM having offset vertical transistors and method DRAM having offset vertical transistors and method

2003-01-14

2004-04-27

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S240000, C438S241000, C438S243000, C257S301000, C257S302000

Reexamination Certificate

active

06727141

ABSTRACT:

TECHNICAL FIELD
The field of the invention is that of forming vertical field effect transistors, in particular, in closely packed DRAM cells, while avoiding adverse effects from the reduced distance between cells.
BACKGROUND OF THE INVENTION
As dimensions in integrated circuits shrink, new problems arise and old solutions to previous problems break down. In the particular case of DRAM arrays based on trench capacitors with vertical access transistors, a problem that has become significant is that of “back to back” buried straps.
Those skilled in the art are aware that DRAM cells based on a trench capacitor with a pass transistor formed in vertical orientation on the inner wall of the trench is very compact—present technology being an 8F
2
cell (F being the symbol for the minimum lithographic dimension).
The trench process formation produces a compact cell because the trench process essentially trades depth for area. The trench is etched very deeply—several microns—that provides surface area for the capacitor plates that does not take up silicon real estate on the surface.
The standard structure of a trench DRAM cell makes the connection between the capacitor electrode through a conductive element referred to as a buried strap that is placed on the top surface of the center electrode of the capacitor and makes contact with the source/drain of the vertical transistor in the upper part of the trench (the source/drain being formed in the single-crystal substrate) by a diffusion that extends vertically from the capacitor to the transistor channel.
Inevitably, the diffusions also extends transversely. As distances between cells shrink, there is potential difficulty from the interaction of diffusions in adjacent cells. The buried strap process does not have some of the possibilities of flexibility in geometry that are available for DRAM cells having horizontal cells with the buried strap close to the surface, since implantation and shaping the strap horizontally by a mask are not options.
Since the buried strap has a DC voltage that is the same as the capacitor, it adds a potential source of leakage.
With the shrinking of distances between cells and the reduction in dopant concentration in the P-well (done for improved retention), it can happen that the outdiffusion and depletion region from one buried strap can extend far enough toward the adjacent cell that the substrate near the vertical transistor can be isolated from the bulk wafer substrate, becoming a floating body. As a result, the thresholds of vertical transistors become unstable and can affect DRAM cell operation by reduction of the retention time.
The retention time of a DRAM cell is very important for the operation of the DRAM system, since frequent refreshing of the cells reduces the time that is available for the main purpose of the DRAM—accessing the memory cells.
SUMMARY OF THE INVENTION
The invention relates to a DRAM array in which adjacent cells on the same bitline have buried straps that are at different levels, thus increasing the distance between the buried straps.
A feature of the invention is recessing the center electrode in alternate cells, forming buried straps alternately at different heights and forming vertical transistors having the same channel length in both types of cell, thus increasing the distance between the straps of the adjacent cells.
In another embodiment of the invention top strap conductive regions of different height are formed, with a longer strap over the lower transistor, to connect the upper electrode of the transistor to the contact formed in the top surface of the semiconductor.
In another embodiment of the invention buried straps of different vertical heights are formed, connecting to vertical transistors placed at the same height beneath the semiconductor surface.


REFERENCES:
patent: 6172390 (2001-01-01), Rupp et al.
patent: 6255683 (2001-07-01), Radens et al.
patent: 6391705 (2002-05-01), Hsiao et al.
patent: 6515327 (2003-02-01), King
patent: 6566190 (2003-05-01), Lee et al.
patent: 2003/0062562 (2003-04-01), Goebel et al.
patent: 2003/0132438 (2003-07-01), Jang
patent: 2003/0181016 (2003-09-01), Shu

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