DRAM having multiple column address strobe operation

Details DRAM having multiple column address strobe operation DRAM having multiple column address strobe operation

1996-11-14

1997-12-30

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518908, 36523008, 3652385, 3652335, G11C 700, G11C 800

Patent

active

057038139

ABSTRACT:
A dynamic memory device is described which has multiple column address signal inputs. Data can be stored in the memory and selectively read therefrom. The column address signals are used to control the data communication. During a read operation, any one of the multiple column address signal inputs can be used to output data on all external communication lines. During a write operation, each column address signal input writes data from a portion of the external communication lines to the memory device.

REFERENCES:
patent: 5331593 (1994-07-01), Merritt et al.
patent: 5349566 (1994-09-01), Merritt et al.
patent: 5457659 (1995-10-01), Schaefer et al.
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5546344 (1996-08-01), Fawcett
patent: 5598376 (1997-01-01), Merritt et al.
patent: 5610864 (1997-03-01), Manning

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