DRAM for texture mapping

Details DRAM for texture mapping DRAM for texture mapping

1995-12-15

1997-12-30

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365195, 365222, 36523004, 36523005, G11C 700

Patent

active

057038104

ABSTRACT:
A latch/mask mechanism that is located between the sense amplifiers of a DRAM and the data bus. The latch/mask mechanism decouples the data bus from the sense amplifiers and permits innovative, time saving functionality during read and write operations. During a write operation, the latch can receive only those byte(s) or a row of bytes to be written. Corresponding mask bits are set to indicate those bytes to be written. Logic in the device transfers only those bytes in the row to be written to the sense amplifiers for writing to memory, leaving the data of remaining bytes in memory intact. Read operations are rendered more efficient by enabling logic, coupled to column select logic, to automatically transfer from the latch the byte selected by the column select logic and the adjacent byte. This time saving feature is particularly useful for computer graphics applications which utilize linear interpolation processes.

REFERENCES:
patent: 5568428 (1996-10-01), Toda

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