DRAM device with a refresh period that varies responsive to...

Details DRAM device with a refresh period that varies responsive to... DRAM device with a refresh period that varies responsive to...

2007-02-13

2007-02-13

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189070, C365S189090, C365S191000, C365S149000

Reexamination Certificate

active

11117159

ABSTRACT:
A semiconductor device includes a DRAM and a temperature sense circuit. The DRAM has a refresh period that varies responsive to a temperature signal. The temperature sense circuit is configured to generate the temperature signal having a first binary value in response to sensing a temperature of the DRAM of at least a first temperature level, and to generate the temperature signal having a second binary value in response to sensing a temperature of the DRAM of less than a second temperature level, wherein the second temperature value is less than the first temperature value.

REFERENCES:
patent: 5278796 (1994-01-01), Tillinghast et al.
patent: 6438057 (2002-08-01), Ruckerbauer
patent: 7035157 (2006-04-01), Chang
patent: 63-205713 (1988-08-01), None
patent: 000002015 (2000-01-01), None
patent: 1020030011395 (2003-02-01), None
patent: 10-2004-0013885 (2004-02-01), None
Notice to Submit a Response for Korean Patent Application No. 10-2004-004416 mailed on Nov. 24, 2005.

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