DRAM configuration in PLDs

Details DRAM configuration in PLDs DRAM configuration in PLDs

1998-01-30

1999-11-16

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Data refresh

365154, 365156, G11C 700

Patent

active

059869585

ABSTRACT:
Described are dynamic memory cells for use in FPGAs. Each memory cell includes a dynamic memory element that occupies less chip area than conventional static memory elements and that can be implemented using standard CMOS processes. In one embodiment, a conventional access transistor is connected to a pass transistor via a CMOS inverter. The CMOS inverter includes a pair of complementary MOS transistors sharing a common gate connection, and therefore exhibiting a combined gate capacitance. This gate capacitance at the input of the inverter supplements or replaces the capacitor normally required in conventional dynamic memory cells. Another embodiment uses the parasitic gate capacitance of a pass transistor for dynamic data storage. This embodiment requires that the voltage levels on the source and drain of the pass transistor be controlled during write and refresh operations to ensure that the gate capacitance of pass transistor stores an appropriate level of charge.

REFERENCES:
patent: 4750155 (1988-06-01), Hsieh
patent: 4821233 (1989-04-01), Hsieh
patent: 5771189 (1998-06-01), Jun et al.
patent: 5835403 (1998-11-01), Forbes
patent: 5838606 (1998-11-01), Blankenship et al.

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