DRAM circuit and its operation method

Details DRAM circuit and its operation method DRAM circuit and its operation method

2006-02-14

2006-02-14

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S063000

Reexamination Certificate

active

06999364

ABSTRACT:
A high-density DRAM in a MTBL method which reduces interference noise between bit lines is provided. Duplication of sense amplifiers (SA) and bit switches (BSW) in a conventional MTBL method is eliminated, and one line of sense amplifiers and bit switches (BSW/SA) is arranged between cell areas. Specifically, arrays are horizontally moved and vertically cumulated so as to reduce the areas. Bit line pairs to be connected are alternately interchanged above and below, every one horizontally aligned sense amplifier (SA). Bit lines of a bit line pair11cross at one place on the way, and from the cross, a space between the bit lines is wider. Further, bit lines of a bit line pair16do not cross each other, and a space between the bit lines is wider on the way. In a new MTBL method, both in the bit lines connected to the same sense amplifier and in the bit lines among adjacent bit lines connected to the different sense amplifiers, a space between the bit lines changes (widens or narrows) before and after the cross. Thus, the interference noise between any adjacent bit lines is decreased.

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Article: IEEE Journal of Solid-State Circuits, vol. 34, No. 6, Jun. 1999 “Multiple Twisted Dataline Techniques for Multigigabit DRAMs's”, by Dong-Sun Min, pp. 856-865.
Article in ISSCC 2002 Digest of Technical Papers, Sessin 9, 9.3 “A 300MHz Multi-banked eDRAM Macro Featuring GND Sense, Bit-Line Twisting and Direct Reference Cell Write” by John Barth, Darren Anand, Jeff Dreibelbis, Erik Nelson pp. 156-157.

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