DRAM chip fabrication method

Details DRAM chip fabrication method DRAM chip fabrication method

1998-08-26

2001-03-27

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S241000, C257S315000, C257S408000

Reexamination Certificate

active

06207500

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to semiconductor devices, and more particularly to an improved method for forming a DRAM chip.
BACKGROUND OF THE INVENTION
In the fabrication of dynamic random access memory (DRAM) arrays, gate material is typically patterned onto an insulating layer above a channel region. The gate material is typically surrounded by an insulating dielectric material deposited on top of the gate, with thin sidewalls extending down both sides of the gate. The dielectric material serves to insulate the gate from self-aligned source and drain contacts formed on either side of the gate.
In a DRAM array, the thickness of the insulating sidewalls is typically determined by the design rule and pitch of the array. For example, for a 0.3 micron design rule and a 0.6 micron pitch design, the sidewall thickness may be 500-700 Angstroms. For smaller design rules, the sidewall thickness may decrease to less than 300 Angstroms.
The DRAM array is typically surrounded on a chip by peripheral circuitry that includes metal oxide semiconductor field effect transistors (MOSFETs). To maximize efficiency in chip manufacturing, the gate deposition and insulating steps used in forming the DRAM array are typically used to simultaneously form the peripheral MOSFET gates. As a result, the sidewalls insulating the peripheral MOSFET gates will have the same thickness as the sidewalls in the DRAM array.
This peripheral sidewall thickness may not be the optimal thickness for MOSFET gate insulating sidewalls. For example, a source/drain implant is typically performed for peripheral MOSFETs after formation of the gate and insulating sidewalls, to separate the heavily doped portions of the source and drain regions from the channel region. This separation is necessary to prevent lateral diffusion of the source/drain dopant into the channel, and to reduce stress on the MOSFET device due to high electric fields at the source-channel junction and drain-channel junction.
Thus, if the design rule of the DRAM array does not allow for sufficiently thick sidewalls in the peripheral area, the physical channel lengths of the peripheral MOSFETs may have to be increased to maintain a given effective channel length due to lateral diffusion into the channel. Performance of the peripheral MOSFETs may also be affected due to increased stress at the source-channel and drain-channel junctions.
SUMMARY OF THE INVENTION
Therefore, a need has arisen for a DRAM chip fabrication method that addresses the disadvantages and deficiencies of the prior art.
An improved method for forming a DRAM chip is disclosed. According to this method, a memory cell gate is deposited in a memory cell array area of the DRAM chip. The memory cell gate overlies a first channel area of a substrate. A peripheral gate is deposited in a peripheral area of the DRAM chip. The peripheral gate overlies a second channel area of the substrate. A first dopant is implanted with a first concentration in a first plurality of source and drain regions of the substrate lying predominantly outside the first and second channel areas of the substrate. A sidewall is then formed adjacent to the peripheral gate. Simultaneously, an insulating layer is formed over the memory cell array area of the DRAM chip. A second dopant is implanted with a second concentration in a second plurality of source and drain regions of the substrate within the peripheral area of the DRAM chip. The implant of the second dopant is blocked by the sidewall and the insulating layer.
In one embodiment of the present invention, the first and second dopants are the same, and the dopant concentration in the second plurality of regions is greater than the dopant concentration in the first plurality of regions.
A technical advantage of the present invention is that the method allows the formation of more heavily doped source and drain regions in the peripheral area of the DRAM chip while keeping the heavily doped regions separated from the channel regions. Another technical advantage is that diffusion into the channel regions is reduced, which allows a smaller design rule to be used. Another technical advantage is that stress at the source-channel and drain-channel junctions may be reduced. Furthermore, the above-described method has no impact on the formation of the DRAM cell array itself. Yet another technical advantage is that, because the added steps of this method are self-aligning in nature, the “masking level” of the overall DRAM chip fabrication process is not increased.


REFERENCES:
patent: 5324680 (1994-06-01), Lee et al.

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