DRAM cell with vertical CMOS transistor

Details DRAM cell with vertical CMOS transistor DRAM cell with vertical CMOS transistor

2000-04-24

2001-12-04

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S387000, C438S388000, C438S243000, C438S244000, C438S245000

Reexamination Certificate

active

06326275

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is integrated circuit processing, in particular circuits containing a DRAM array employing trench capacitors.
BACKGROUND OF THE INVENTION
In DRAMs and embedded DRAMs, the art has constantly sought to decrease the size of the one-transistor one-capacitor cell. Cells that place the transistor on the wall of a trench capacitor have been tried but without success. Among other problems, the transistor is quite leaky, which is unacceptable in DRAMs.
SUMMARY OF THE INVENTION
The invention relates to a method of forming a DRAM cell with an integrated vertical transistor.
A feature of the invention is the deposition of a protective doped poly layer on the trench walls that protects the walls during buried strap formation.
Another feature of the invention is the simultaneous removal of the protective layer and the filler material in the trench, thereby avoiding the need for an extra removal step.


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