DRAM cell with enhanced capacitor area and the method of...

Details DRAM cell with enhanced capacitor area and the method of... DRAM cell with enhanced capacitor area and the method of...

2011-06-02

2011-12-27

Menz, Douglas (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S251000

Reexamination Certificate

active

08084321

ABSTRACT:
A dynamic random access memory (DRAM) cell and the method of manufacturing the same are provided. The DRAM cell includes a cell transistor and a cell capacitor. The cell capacitor includes a first, second and third dielectric layer, and a first, second and third capacitor electrode. The first dielectric layer is located on a first capacitor electrode. The second capacitor electrode is located on top of the first dielectric layer. The second dielectric layer is located on the second capacitor electrode. The third capacitor electrode is located on the second dielectric layer and is electrically connected with the drain. The third dielectric layer is located between the third capacitor electrode and the gate for isolating the gate from the third capacitor electrode.

REFERENCES:
patent: 4864464 (1989-09-01), Gonzalez
patent: 6569717 (2003-05-01), Murade
patent: 6847076 (2005-01-01), Tsou
patent: 1027884 (1998-01-01), None

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