DRAM cell transistor device and method

Details DRAM cell transistor device and method DRAM cell transistor device and method

2011-08-02

2011-08-02

Pert, Evan (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S186000, C438S238000, C438S276000, C438S653000, C257S272000, C257S296000, C257SE27084, C257SE21647, C257SE21061

Reexamination Certificate

active

07989284

ABSTRACT:
A method for forming a memory device. The method provides a protective layer overlying a surface region of a substrate before threshold voltage implant. The method then includes depositing a photo resist layer and patterning the photo resist by selectively removing a portion of the photo resist to expose the protective layer overlying a first region while maintaining the photo resist overlying a second region. The method includes implanting impurities for threshold voltage adjustment into the first region while the second region is substantially free of the impurities for threshold voltage adjustment. The method also includes forming a source region and a drain region. The method further includes providing a conductive structure over the source region. A junction between the conductive structure and the source region is substantially within the second region. The method then provides a storage capacitor in electrical contact with the source region via the conductive structure.

REFERENCES:
patent: 5861334 (1999-01-01), Rho
patent: 2001/0054734 (2001-12-01), Koh et al.
patent: 2008/0272408 (2008-11-01), Vora
Office Action of Chinese Application No. 200710094551.9 dated Dec. 4, 2009, 5 pages total (English translation not included).

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