DRAM cell system and method for producing same

Details DRAM cell system and method for producing same DRAM cell system and method for producing same

2001-05-11

2003-05-20

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S249000

Reexamination Certificate

active

06566187

ABSTRACT:

DESCRIPTION
DRAM cell arrangement and method for fabricating it
The invention relates to a DRAM cell arrangement and a method for fabricating it.
Endeavors are generally made to produce a DRAM cell arrangement with an ever higher packing density.
EP 0 852 396 describes a DRAM cell arrangement in which, in order to increase the packing density, a transistor of a memory cell is arranged above a storage capacitor of the memory cell. Active regions of the memory cells are in each case surrounded by an insulating structure arranged in a substrate. A depression is produced in the substrate for each memory cell, a storage node of the storage capacitor being arranged in the lower region of the said depression and a gate electrode of the transistor being arranged in the upper region of said depression. An upper source/drain region, a channel region and a lower source/drain region of the transistor are arranged one above the other in the substrate. The lower source/drain region is connected to the storage node at a first sidewall of the depression. The insulating structure adjoins a second sidewall—opposite to the first sidewall—of the depression, with the result that the storage node does not adjoin the substrate there. A capacitor electrode of the storage capacitor is formed by the addiffusion of dopant into the substrate. A lower region of the depression is widened by an isotropic etching process, areas of the upper region being protected in the process. As a result, a horizontal cross section of the lower region has a larger area than a horizontal cross section of the upper region. By virtue of the widening of the lower region of the depression, the surface area of a capacitor dielectric is enlarged and the capacitance of the storage capacitor is thus increased. A bit line adjoins the upper source/drain region and runs above the substrate. The depression is produced by etching the substrate selectively with respect to the bit lines with the aid of a strip-shaped mask whose strips run perpendicularly to the bit lines. A word line is produced together with a gate electrode by material being deposited in the upper region of the depression and being patterned. The gate electrode is insulated from the substrate and from the bit lines by a gate dielectric and by the insulating structure.
German patent specification 195 19 160 describes a DRAM cell arrangement in which a storage capacitor is arranged above a vertical transistor. With the aid of a mask widened by spacers, first trenches are produced, which cut through a layer sequence and are filled with a first insulation structure. Second trenches are then produced, which run transversely with respect to the first trenches and are shallower and wider than the first trenches. The second trenches are filled with a second insulation structure. The insulation structures are etched back to produce a lattice-shaped depression. After the production of the gate dielectric, in order to produce word lines, conductive material is deposited and etched back, with the result that, on account of the different widths of the trenches, the word lines are produced in a self-aligned manner in such a way that they run parallel to the second trenches. Parts of the layer sequence which are surrounded by the word lines act as the transistors. A capacitor dielectric is produced above the word lines and layer sequence, and a capacitor plate of the storage capacitors is produced above said capacitor dielectric. Upper parts of the layer sequence act as upper source/drain regions of the transistors and, at the same time, as capacitor electrodes of the storage capacitors. The memory cell can be fabricated with an area of 4F
2
, where F is the minimum feature size that can be fabricated in the technology used. Lower parts of the layer sequence act as bit lines which are isolated from one another by the first insulation structures and run parallel to the first trenches. Neither the word lines nor the bit lines have a high electrical conductivity.
The invention is based on the problem of specifying a DRAM cell arrangement whose word lines and bit lines can have a high electrical conductivity and which can, at the same time, be fabricated with a high packing density. Furthermore, the intention is to specify a method for fabricating it.
The problem is solved by means of a method for fabricating a DRAM cell arrangement, in which firstly first trenches running essentially parallel to one another are produced in a substrate. The first trenches are filled with isolating structures. By etching with the aid of a strip-shaped photoresist mask whose strips run transversely with respect to the first trenches, the substrate is etched selectively with respect to the isolating structures, with the result that depressions are produced. Areas of lower regions of the depressions are provided with a capacitor dielectric. A storage node of a storage capacitor is in each case produced in the lower regions of the depressions. Upper source/drain regions of the transistors are produced in such a way that they are in each case arranged between two mutually adjacent depressions of the depressions and between two mutually adjacent isolating structures of the isolating structures, and adjoin a main area of the substrate. At least first side walls of the depressions are provided with a gate dielectric in upper regions of the depressions. Lower source/drain regions of the transistors in the substrate are formed in such a way that they are electrically connected to the storage nodes, with the result that in each case one of the transistors and one of the storage capacitors are connected in series and form a memory cell. By depositing and patterning conductive material, word lines are produced, which run transversely with respect to the isolating structures and above the main area, and, adjoining them, gate electrodes of vertical transistors are produced, which are each arranged in one of the depressions and are electrically insulated from the storage nodes. An insulating layer is produced over the word lines. Insulating spacers are produced on side walls of the word lines by depositing material and etching it back. With the aid of a strip-shaped photoresist mask whose strips run essentially parallel to the isolating structures, etching is effected selectively with respect to the insulating layer and the spacers until the upper source/drain regions are uncovered. Bit lines are produced which make contact with the upper source/drain regions.
The problem is furthermore solved by means of a DRAM cell arrangement, in which a depression is provided in a substrate for a memory cell. The depression is arranged between strip-shaped isolating structures. Areas of a lower region of the depression are provided with a capacitor dielectric of a storage capacitor. A storage node of the storage capacitor is arranged in the lower region of the depression. A lower source/drain region of a vertical transistor is arranged in the substrate and is electrically connected to the storage node, with the result that the transistor and the storage capacitor are connected in series and form the memory cell. A first side wall of the depression is provided with a gate dielectric in an upper region of the depression. A gate electrode of the transistor is arranged in the upper region of the depression, said gate electrode being electrically insulated from the storage node. A word line runs above a main area of the substrate and transversely with respect to the isolating structures and adjoins the gate electrode. An insulating layer is arranged over the word line. Side walls of the word line are provided with insulating spacers. A bit line runs transversely with respect to the word line. Parts of the bit line are arranged between the spacers of mutually adjacent word lines and adjoin upper source/drain regions of the transistors of memory cells which are arranged on the main area of the substrate. The upper source/drain regions are isolated from one another by the depressions and the isolating structures and adjoin them.
The inventi

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