DRAM cell having tunnel shaped structure and formation process t

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257296, 257309, 257368, 257390, 257401, H01L 2701, H01L 2713, H01L 2978

Patent

active

052626636

ABSTRACT:
A DRAM cell having a tunnel-shaped structure (in the form of buried bit line structure) and a formation process therefore are disclosed. A storage poly and a local connecting layer are interconnected in such a manner as to form a tunnel-shaped portion, and a bit line passes through the tunnel formed by the combination of the local connecting layer and the storage poly. A flattening insulating layer, a bit line capping-oxide-layer and a spacer are filled between the storage poly, the local connecting layer and the bit line. The storage poly is contacted through the local connecting layer to a first semiconductor region, while the bit line is directly contacted to a second semiconductor region.

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