DRAM cell having electrode with protection layer

Details DRAM cell having electrode with protection layer DRAM cell having electrode with protection layer

2002-07-08

2004-03-09

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S326000, C438S024000, C438S306000

Reexamination Certificate

active

06703657

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 99-48926, filed on Nov. 5, 1999, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a method for fabricating such a device. More particularly, the present invention relates to a DRAM cell and a method for fabricating such a DRAM.
Semiconductor memories are considered one of the crucial microelectronics components for mainframe computers, PCs, telecommunications, automotive and consumer electronics, and commercial and military avionics systems. Semiconductor memory devices can be characterized as either volatile random access memory devices (RAMs) or non-volatile memory devices (NVMs). RAMs can further include dynamic RAMs (DRAMs) and static RAMs (SRAMs). As is well known, DRAMs have about four times as high a degree of integration compared to SRAMs. Because of this, DRAMs have been widely used in computer main memories.
DRAMs are composed of a cell array region that has a plurality of memory cell arrays, and a peripheral circuit region that controls and drives the memory cell arrays. Each memory cell typically consists of a cell storage capacitor and an access transistor. Either the source or drain of the access transistor is connected to one terminal of the cell capacitor. The properties of the cell storage capacitor directly affects the characteristics of the DRAM, such as data retention, soft error rate, low voltage performance, or the like. In particular, a higher capacitance of the cell capacitor improves the data retention characteristics and low voltage characteristics, and reduces the soft error rate of the DRAM. Accordingly, in order to realize high density DRAM devices, the cell capacitor is formed to have an acceptable level of capacitance in a given cell.
U.S. Pat. No. 5,597,756 by Fazan et al entitled as “PROCESS FOR FABRICATING A CUP-SHAPED DRAM CAPACITOR USING A MULTI-LAYER PARTIALLY-SACRIFICIAL STACK”, the disclosure of which is incorporated herein by reference, discloses a capacitor storage node having HSG silicon layer on its surface. Also, U.S. Pat. No. 5,907,772 by Iwazaki entitled as “METHOD FOR PRODUCING CYLINDRICAL STORAGE NODE OF STACKED CAPACITOR IN MEMORY CELL”, the disclosure of which is incorporated herein by reference, discloses a planarized interlayer insulating layer formed on a semiconductor substrate. The semiconductor substrate has an access transistor and a cylindrical storage node formed on the planarized interlayer insulating layer, which is electrically connected to a source region of the access transistor.
FIGS. 1
to
5
are cross-sectional views of a conventional semiconductor substrate, at selected stages of a DRAM fabrication process. Referring to
FIG. 1
, a device isolation region
23
is formed in a predetermined region of a semiconductor substrate
21
to define an active region. A gate oxide layer
25
is formed on the active region. Doped polysilicon and a silicon nitride layers are sequentially formed on the resulting structure. The doped polysilicon and the silicon nitride layers are patterned to form a first and a second gate patterns
30
a
and
30
b
, intersecting the active region and neighbouring each other. The first gate pattern
30
a
comprises a stacked layer of a first polysilicon pattern
27
a
and a first silicon nitride layer pattern
29
a
. Similarly, the second gate pattern
30
b
comprises a stacked layer of a second polysilicon pattern
27
b
and a second silicon nitride layer pattern
29
b
. The first and second polysilicon patterns
27
a
and
27
b
respectively serve as a gate electrode of neighbouring access transistors.
A silicon nitride layer is formed on the entire surface of the semiconductor substrate
21
having the first and second gate patterns
30
a
and
30
b
and is then anisotropically etched to form a side wall spacer
31
on side walls of the first and second gate patterns
30
a
and
30
b.
Referring now to
FIG. 2
, an insulating layer
33
, such as a CVD oxide layer, is formed on the resulting structure. Selected portions of the insulating layer
33
are then etched to form pad contact holes that respectively expose the active regions outside of the first and second gate patterns
30
a
and
30
b
. A contact hole, defined between the first and second gate patterns
30
a
and
30
b
, is a bit line pad contact hole. Contact holes outside of the bit line pad contact hole are respectively first and second storage node pad contact holes, respectively. A bit line pad
35
d
and first and second storage node pads
35
a
and
35
b
are formed by respectively filling the bit line pad contact hole and the first and second storage node pad contact holes with a conductive material.
Referring now to
FIG. 3
, a first interlayer insulating layer
37
, such as a CVD oxide, is formed on the resulting structure. A selected portion of the first interlayer insulating layer
37
is then etched to form a bit line contact hole (not shown), which exposes the bit line pad
35
d
. The bit line contact hole is then filled with a conductive material to form a bit line (not shown). A second interlayer insulating layer
39
, an etching stopper layer
41
, and a sacrificial insulating layer
43
are then sequentially formed on the first interlayer insulating layer
37
including the bit line. The second interlayer insulating layer
39
comprises a CVD oxide layer planarized by CMP process. The etching stopper layer
41
comprises a material having an etching selectivity with respect to an oxide, such as a silicon nitride layer. The sacrificial insulating layer
43
comprises a CVD oxide.
Referring now to
FIG. 4
, the sacrificial insulating layer
43
, the etching stopper layer
41
, the second interlayer insulating layer
39
, and the first interlayer insulating layer
37
are sequentially patterned to form first and second storage node holes
45
a
and
45
b
, respectively exposing the first and second storage node pads
35
a
and
35
b
. At this time, the first and second storage nodes holes
45
a
and
45
b
can be misaligned to the storage node pads
35
a
and
35
b
, thereby exposing the bit line pad
35
d
, as shown in FIG.
4
.
A conformal conductive layer is deposited on the sacrificial insulating layer
43
and in the holes
45
a
and
45
b
to form first and second cylindrical storage nodes
47
a
and
47
b
. As noted above, in the case of a misalignment of the first and second storage node holes
45
a
and
45
b
, one of the first and second storage nodes
47
a
and
47
b
, for example, the second storage node
47
b
, becomes electrically connected to the bit line pad
35
d.
Referring to
FIG. 5
, the sacrificial insulating layer
43
is etched to expose outer sidewalls of the first and second cylindrical storage nodes
47
a
and
47
b
. The etching stopper layer
41
serves as an end-point of the etching and thus the second interlayer insulating layer
39
is not exposed.
As described above, when misalignment occurs during a photolithography process for forming storage node holes, the storage node and the bit line pad may be electrically connected, causing a malfunction of the fabricated DRAMs.
SUMMARY OF THE INVENTION
The present invention was made in view of above-mentioned problems and it is an object of the present invention to provide a method of fabricating a DRAM cell that can prevent bit line pad from being exposed by the storage node hole even when there is misalignment of the storage node hole during a photolithography process.
It is another object of the present invention to provide a method of fabricating a high performance cell capacitor compatible with high density DRAMs.
It is still another object of the present invention to provide a DRAM cell in which the storage node and the bit line pad are electrically separated even when there is misalignment of the storage node hole to the bit line.
In accordance with the present invention, a method is provided for fabricating a cylindrical capacitor. The met

Affiliated with

Also associated with

Rating

DRAM cell having electrode with protection layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM cell having electrode with protection layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM cell having electrode with protection layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3217080