Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-15
2001-12-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S239000, C438S386000, C438S387000, C257S296000
Reexamination Certificate
active
06329239
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a dynamic random access memory (hereinafter, abbreviated as DRAM) cell structure of a one-structure of a transistor and capacitor type and a manufacturing method thereof; and, more specifically, to a DRAM cell structure and a manufacturing method thereof which are capable of effectively reducing a cell area and simplifying the fabrication process with an sufficient cell capacitance to thereby obtain a highly integrated DRAM and the reliability thereof.
DESCRIPTION OF THE PRIOR ART
In a conventional dynamic random access memory, there are provided a plurality of memory cells arranged in a matrix array. Each of the memory cell includes a transistor and a capacitor. With increasing the capacity of memory, a cell structure of the DRAM device has a tendency to adopt a three-dimensional from rather than a planner form.
In order to increase the capacity of the memory by reducing a cell area, various devices and methods have been developed. For example, one of those devices is disclosed in an article by W. F. Richardson et al., “A Trench Transistor Cross Point DRAM Cell”,
IEDM
85 (1985
IEEE International Electron Device Meeting
), IEDM Tech. Dig. 1985, pp 714-717, which has one-transistor and a capacitor formed vertically in a deep trench. The capacitor is composed of a charge storage electrode and a surrounding substrate portion thereof. A dielectric film is sandwiched therebetween. The substrate portion surrounding the lower portion of the trench is used as the common capacitor electrode for all cells and is called a plate. The structure of the device utilizes the capacitor which is formed deep in the trench below the transistor. Therefore, the effective capacitance of the memory cell can be easily increased with increasing depth of the trench within a limited cell area, resulting a highly integrated DRAM. However, the above structure has problems such that, since a recessed oxide isolation and a drain region of cell are formed around an upper porion of a trench, a recessed oxide isolation requires a specified distance between neighboring drain regions, thus limiting an achievable minimum gap distance between cells. Further, if a short gap between cells is selected, a punch-through phenomenon between the drain regions may occur, thus resulting in a memory failure or information error.
Another improved structure for a DRAM is disclosed in U.S. Pat. No. 5,001,526 issued on Mar. 19, 1991, to Hiroshi Gotou, which includes memory cells formed on an insulating layer, each memory cell having a buried semiconductor pillar structure. The lower portion of the semiconductor pillar is used as a storage electrode of a capacitor and the upper porion thereof is used as active regions of a transistor. Specifically, the cell plate of the capacitor is formed around side surfaces of the lower portion of the semiconductor pillar, together with dielectric film therebwteen.
However, although the cell structure may successfully solves the above gap distance problem between cells, it is substantially difficult to obtain the effective capacitance of the memory cell because the lower portion of the charge storage electrode is directly coupled to the insulating layer and a polysilicon formed around the side surfaces thereof merely functions as the cell plate of the capacitor. It is, therefore, difficult to obtain a sufficient degree of reliability. Furthermore, since the pillar structure is formed by employing a complex epitaxial growth, it should be needed that a further simplified fabrication process is subjected to form DRAM cell structure having an effectively reduced cell area and an sufficient cell capacitance to thereby obtain a highly integrated DRAM.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the invention to provide a DRAM cell structure and a manufacturing method thereof which are capable of effectively reducing a cell area and simplifying the fabrication process with an sufficient cell capacitance to thereby obtain a highly integrated DRAM and its reliability.
In accordance with one aspect of the present invention, there is provided a method for preparing a semiconductor device having a plurality of memory cells in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel, which comprises the steps of: (a) forming a plurality of first junction regions on a first semiconductor wafer, each first junction region surrounded by a isolation layer; (b) forming a plurality of cylindrical charge storage electrodes, each cylindrical charge storage electrode containing side surfaces, an upper portion and a lower porion, and the upper portion of the cylindrical charge storage electrode coupled to a corresponding first junction region; (c) forming a dielectric layer over the side surfaces and lower surface of each of the cylindrical charge storage electrode; (d) forming a plate electrode surrounding an entire surface of the dielectric layer for said each cylindrical charge storage electrode; (e) forming a first insulation layer on the plate electrode by making a surface of the plate electrode flat; (f) bounding a second semiconductor wafer to the first insulation layer whereby the first semiconductor is supported by the second semiconductor; (g) forming a plurality of vertical channels by polishing and selectively etching the first semiconductor wafer having a predetermined thickness, each vertical channel coupled to the corresponding first junction region; (h) forming a gate electrode surrounding said each vertical channel, wherein the gate electrode has a gate insulator located between the gate electrode and said each vertical channel; (i) forming a second junction region on a upper surface of said each vertical channel; (j) forming a number of bit line by forming and selectively etching a second insulation layer on a resultant structure from the above steps and by forming and selectively etching a metal layer over the etched second insulation layer, each bit line coupled to a predetermined number of the second junction regions arranged on a line.
In accordance with another aspect of the present invention, there is provided a semiconductor memory device prepared by a method recited in claim
1
and having a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel, said each memory cell comprising: a first junction region surrounded by the field oxide layer; a vertical channel including side surfaces, an upper portion and a lower portion, the lower portion of the vertical channel coupled to the first junction region; a second junction region coupled to the upper potion of the vertical channel; a gate electrode surrounding the side surfaces of the vertical channel and including a gate insulator located between the gate electrode and the side surfaces of the vertical channel; a charge storage electrode containing side surfaces, an upper portion and lower portion, the upper potion of the charge storage electrode coupled to the first junction region; a dielectric layer formed on the lower porion and the side surfaces of the charge storage electrode; and a plate electrode entirely surrounding the dielectric layer.
REFERENCES:
patent: 5001526 (1991-03-01), Gotou
patent: 5004705 (1991-04-01), Blackstone
patent: 5389559 (1995-02-01), Hsieh et al.
patent: 5710056 (1998-01-01), Hsu
patent: 5780341 (1998-07-01), Ogura
patent: 5888864 (1999-03-01), Koh et al.
patent: 5914510 (1999-06-01), Hieda
patent: 6045625 (2000-04-01), Houston
patent: 6074892 (2000-06-01), Bowers et al.
patent: 0282716 (1988-09-01), None
Choi Jin Hyeok
Kang Sang Won
Koh Yo Hwan
Blakely & Sokoloff, Taylor & Zafman
Hyundai Electronics Industries Co,. Ltd.
Lee, Jr. Granvill D.
Smith Matthew
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