DRAM cell constructions, and methods of forming DRAM cells

Details DRAM cell constructions, and methods of forming DRAM cells DRAM cell constructions, and methods of forming DRAM cells

2000-08-30

2002-08-06

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000

Reexamination Certificate

active

06429070

ABSTRACT:

TECHNICAL FIELD
The invention pertains to DRAM cell constructions and methods of forming DRAM cells.
BACKGROUND OF THE INVENTION
Technologies referred to as “smart cut” and “wafer-bonding” have been utilized to bond monocrystalline silicon materials onto semiconductor substrates. Smart cut technology generally refers to a process in which a material is implanted into a silicon substrate to a particular depth and ultimately utilized to crack the substrate, and wafer bonding technology generally refers to a process in which a first semiconductive substrate is bonded to a second semiconductor substrate.
In particular applications of smart cut and wafer-bonding technology, hydrogen ions (which can be, for example, H
+
, H
2
+
, D
+
, D
2
+
) are implanted into a first monocrystalline silicon substrate to a desired depth. The first monocrystalline silicon substrate comprises a silicon dioxide surface, and is bonded to a second monocrystalline substrate through the silicon dioxide surface. Subsequently, the bonded first substrate is subjected to a thermal treatment which causes cleavage along the hydrogen ion implant region to split the first substrate at a pre-defined location. The portion of the first substrate remaining bonded to the second substrate can then be utilized as a silicon-on-insulator (SOI) substrate. An exemplary process is described in U.S. Pat. No. 5,953,622. The SOI substrate is subsequently annealed at a temperature of greater than or equal to 900° C. to strengthen chemical coupling within the second substrate.
The present invention encompasses new applications for smart cut and wafer-bonding technology, and new semiconductor structures which can be created utilizing such applications.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a method of forming a DRAM cell. A first substrate is formed to comprise first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate provided which comprises a monocrystalline material. The second semiconductor substrate is bonded to the first substrate after forming the first DRAM sub-structures. Second DRAM sub-structures are formed on either the first substrate or the second substrate and in electrical connection with the first DRAM sub-structures. Either the first DRAM sub-structures or the second DRAM sub-structures are transistor gate structures, and the other of the first and second DRAM sub-structures are capacitor structures.
In another aspect, the invention encompasses another method of forming a DRAM cell. A first substrate is formed to comprise first DRAM sub-structures separated from one another by an insulative material. The first DRAM sub-structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material. The second semiconductor substrate is bonded to the first substrate above the first DRAM sub-structures. Second DRAM sub-structures are formed on the second substrate and in electrical connection with the first DRAM sub-structures. Either the first DRAM sub-structures or the second DRAM sub-structures are transistor gate structures, and the other of the first and second DRAM sub-structures are capacitor structures.
In yet another aspect, the invention encompasses a semiconductor structure which comprises a cell plate layer, a dielectric material over the cell plate layer, and a conductive storage node mass over the dielectric material. The conductive storage node mass, dielectric material and cell plate layer together define a capacitor structure, and a first substrate is defined to encompass the capacitor structure. The semiconductor structure further comprises a monocrystalline silicon substrate bonded to the first substrate and over the storage node mass. Additionally, the semiconductor structure comprises a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.


REFERENCES:
patent: 4612629 (1986-09-01), Harari
patent: 4891329 (1990-01-01), Reisman et al.
patent: 5298449 (1994-03-01), Kikuchi
patent: 5374564 (1994-12-01), Bruel
patent: 5374581 (1994-12-01), Ichikawa et al.
patent: 5855693 (1999-01-01), Murari et al.
patent: 5877070 (1999-03-01), Goesele et al.
patent: 5882987 (1999-03-01), Srikrishnan
patent: 5894152 (1999-04-01), Jaso et al.
patent: 5953622 (1999-09-01), Lee et al.
patent: 6004406 (1999-12-01), Kobayashi et al.
patent: 6083324 (2000-07-01), Henley et al.
patent: 6150031 (2000-11-01), Yonehara
patent: 6245161 (2001-06-01), Henley et al.
patent: 6251754 (2001-06-01), Ohshima et al.
“Semiconductor Wafer Bonding: Science, Technology, and Applications”; Ulrich Gosele et al.; The Electrochemical Society, Inc.; vol. 97-36; pp. iii, 408-417 & 436-445.

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