Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-15
2002-09-10
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S243000, C438S272000, C438S246000, C438S248000
Reexamination Certificate
active
06448600
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a DRAM cell configuration, that is to say a dynamic random access memory cell configuration, and to a method for fabricating the same.
At the present time, use is made almost exclusively of a so-called one-transistor memory cell, comprising a transistor and a capacitor, as the memory cell of a DRAM cell configuration. The information of the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor, so that when the transistor is driven via a word line, the charge of the capacitor can be read out via a bit line.
A DRAM cell configuration of this type is disclosed in European published patent application EP 0 852 396 A2 for example. A storage node of a capacitor is arranged in a lower region of a depression of a substrate. Above the storage node, a gate electrode of a vertical transistor is arranged in the depression. The gate electrode is insulated by a gate dielectric. Except for a recess in the region of the gate electrode, the storage node is isolated from the substrate by a capacitor dielectric. A lower source/drain region of the transistor is arranged in the region in which the storage node directly adjoins the substrate. An upper source/drain region of the transistor is arranged above the lower source/drain region and adjoins a surface of the substrate and the depression. The upper source/drain region is connected to a bit line.
SUMMARY OF THE INVENTION
The invention is based on the object of specifying a further DRAM cell configuration whose memory cells each have a transistor and a capacitor. It is a further object of the invention to specify a method for fabricating such a DRAM cell configuration.
With the above and other objects in view there is provided, in accordance with the invention, a DRAM cell configuration, comprising:
a plurality of memory cells each having a vertical capacitor and a transistor;
a substrate having formed therein a first depression and a second depression spaced apart from the first depression;
the capacitor being formed as a vertical capacitor having a storage node disposed in the first depression, and a capacitor dielectric in the first depression between the storage node and the substrate;
the storage node adjoining the substrate at least in a contact region of a lateral surface of the first depression;
the transistor having a gate electrode in the second depression at least at a first lateral surface of the second depression;
a gate dielectric adjoining at least the first lateral surface and isolating the gate electrode from the substrate;
the transistor having an upper source/drain region disposed in the substrate adjoining the second depression, and adjoining the storage node in a contact region of the lateral surface of the first depression; and
the transistor having a lower source/drain region disposed deeper in the substrate than the upper source/drain region and adjoining the second depression.
In other words, the DRAM cell configuration has memory cells each having a capacitor and a transistor. The transistor is configured as a vertical transistor. A storage node of the capacitor is arranged in a first depression of the substrate. A capacitor dielectric is arranged in the first depression and is arranged between the storage node and the substrate. The storage node adjoins the substrate at least in a contact region of a lateral surface of the first depression. A second depression of the substrate is provided, which second depression is spaced apart from the first depression. A gate electrode of the transistor is arranged in the second depression at least at a first lateral surface of the second depression and is isolated from the substrate by a gate dielectric, which adjoins at least the first lateral surface. An upper source/drain region of the transistor is arranged in the substrate in such a way that it adjoins the second depression and, in the contact region of the lateral surface of the first depression, the storage node. A lower source/drain region of the transistor is arranged more deeply in the substrate than the upper source/drain region. The lower source/drain region adjoins the second depression.
The object is furthermore achieved by means of a method for producing a DRAM cell configuration in which memory cells each having a capacitor and a transistor are produced. The transistor is produced as a vertical transistor. A first depression is produced in a substrate for the capacitor. The first depression is provided with a capacitor dielectric. A storage node of the capacitor is produced in the first depression. The storage node is produced in such a way that it adjoins the substrate at least in a contact region of a lateral surface of the first depression. A second depression is produced, which is spaced apart from the first depression. A gate electrode of the transistor is produced in the second depression at least at a first lateral surface of the second depression and is isolated from the substrate by a gate dielectric, which is produced such that it adjoins at least the first lateral surface. An upper source/drain region of the transistor is produced in such a way that it adjoins the second depression and, in the contact region of the lateral surface of the first depression, the storage node. A lower source/drain region of the transistor is produced in such a way that it is arranged more deeply in the substrate than the upper source/drain region and adjoins the second depression.
The contact region of the lateral surface of the first depression in which the storage node directly adjoins the upper source/drain region is thus located higher than the lower source/drain region of the transistor.
Since different depressions are provided for the capacitor (storage node) and for the transistor (gate electrode), the first lateral surface of the second depression at which the gate dielectric is produced can escape process steps for producing the first depression. This is advantageous since the quality of a surface area on which the gate dielectric of a transistor is produced generally has a major influence on the electrical properties of the transistor. This surface area is preferably fabricated with particular care, so that the transistor has improved electrical properties.
The provision of two different depressions furthermore affords the advantage that the geometry of the area at which the gate dielectric is produced can be independent of a geometry of an area at which the capacitor dielectric is produced. The area at which the gate dielectric is produced is preferably planar, so that it has a defined orientation with regard to the crystal lattice of the substrate, in order that the gate dielectric can grow homogeneously. By contrast, the area at which the capacitor dielectric is produced is preferably curved, so that the capacitor dielectric has no edges at which field distortions can lead to leakage currents. Accordingly, both the transistor and the capacitor can have particularly good electrical properties.
The first lateral surface of the second depression is preferably planar. A horizontal cross section of the first depression is circular or elliptic, for example.
In order to increase the capacitance of the capacitor, it is advantageous if the first depression is deeper than the second depression.
The gate electrode is connected to a word line.
Part of the substrate which adjoins the first depression acts as a capacitor electrode of the capacitor.
By way of example, the lower source/drain region of the transistor is connected to a bit line running transversely with respect to the word line. As an alternative, the capacitor electrode is connected to the bit line.
In order to improve the driving of the transistor by the gate electrode, it is advantageous if the lower source/drain region at least partly adjoins the first lateral surface of the second depression.
The first lateral surface of the second depression may face away from the first depression. In this case, in comparison with remaining lat
Hofmann Franz
Schlösser Till
Willer Josef
Fourson George
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Pham Thanh
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