Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-08-19
2001-04-10
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S308000
Reexamination Certificate
active
06215143
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a DRAM cell capacitor and a method for manufacturing the same that is capable of increasing capacitance thereof by forming HSG (Hemi-Spherical Grain) on a surface of a storage electrode.
BACKGROUND OF THE INVENTION
Tatsumi discloses a conventional DRAM cell capacitor and manufacturing method in U.S. Pat. No. 5,385,863 issued Jan. 31, 1995, entitled “METHOD OF MANUFACTURING POLYSILICON FILM INCLUDING RECRYSTALLIZATION OF AN AMORPHOUS FILM”. As shown in this application, HSG silicon is grown on a capacitor storage electrode of simple staked structure.
FIG. 1
shows a conventional art DRAM cell capacitor. Referring to
FIG. 1
, a conventional art DRAM cell capacitor has a semiconductor substrate
10
whose active and inactive regions are defined by a field oxide layer
12
. A pad electrode
14
is formed on the active region of the substrate
10
. An interlayer insulating layer
16
is then formed over the field oxide layer
12
including the pad electrode
14
. A contact hole
19
is formed through the interlayer insulating layer
16
to an upper surface of the pad electrode
14
. A conductive layer is then deposited over the interlayer insulating layer
16
to fill up the contact hole
19
, and is then patterned to form a capacitor storage electrode
20
. As the storage electrode
20
is formed it's upper surface is perpendicular to each of its sidewalls.
Next, an HSG silicon layer
22
is formed on the capacitor storage electrode
20
so as to increase an effective surface area. Subsequently, so as to accomplish fabrication of the DRAM cell capacitor, the process steps for sequentially forming a dielectric layer and a capacitor top electrode on the capacitor storage electrode should be followed.
Prior to forming the dielectric layer (not shown) on the capacitor storage electrode, a wet etching and washing process should be performed to remove a part of the interlayer insulating layer
16
and to wash the substrate. Generally, the etching process of the interlayer insulating layer
20
uses an etchant that includes a mixture of NH
4
F and HF (which is called a “Lal solution” in the art), and a mixture of NH
3
, H
2
O
2
and deionized water (which is called an “scl solution” in the arts). The washing process uses an etchant that is a mixture of the scl solution and HF.
During the etching process using scl solution, a part of the HSG silicon layer
22
that is formed on the capacitor storage electrode
20
, particularly, on the top edges thereof is apt to be lifted. When this happens, adjacent capacitor storage electrodes may be electrically connected (i.e., short-circuited) with each other by the lifted HSG silicon.
The short-circuit occurring by the lifted HSG between the storage electrodes is shown in
FIGS. 2A
to
2
C.
FIG. 2A
shows a scanning electron microphotograph (SEM) that illustrates a plan view of the conventional DRAM cell capacitor array,
FIG. 2B
shows a SEM that illustrates a perspective view of the conventional DRAM cell capacitor array shown in FIG.
2
A.
FIG. 2C
is an enlarged perspective view of the two adjacent DRAM cell capacitors which are indicated by a dotted circle in FIG.
2
B.
As is apparent from
FIGS. 2A
to
2
C, after the formation of capacitor storage electrodes, a short-circuit between the capacitor storage electrodes is generated due to an HSG silicon tab
24
, which is lifted from the top edges of the respective capacitor storage electrodes. This leads to the failure of DRAM devices.
Lifting the HSG silicon from the storage electrode is caused by the following two reasons: (1.) HSG silicon which is abnormally grown due to the remaining polymers is apt to be lifted during the etching process of the storage electrode. (2.) HSG silicon which is grown at, particularly, the top edges of the storage electrode is apt to be lifted by the following etching and washing process.
Thus, the present invention relates to a method for manufacturing a DRAM cell capacitor wherein HSG silicon is not formed at the top edges of a storage electrode.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a DRAM cell capacitor that prevents HSG silicon from being formed at the top edges of a storage electrode, and thereby prevents a short-circuit from occurring between storage electrodes due to HSG silicon being lifted from the top edges of the storage electrode, and a method for manufacturing the same.
According to one aspect of the present invention, a DRAM cell capacitor comprises a pad electrode formed over a semiconductor substrate, an interlayer insulating layer formed over the pad electrode, a capacitor bottom electrode formed over the interlayer insulating layer and electrically connected through the interlayer insulating layer to the pad electrode, and an HSG silicon layer formed on a surface of the capacitor bottom electrode. The capacitor bottom electrode has one or more side walls, a top surface, and a top edge formed between the one or more side walls and the top surface and having an angled shape, and the HSG silicon layer is formed only on the top surface and the one or more sidewalls.
The top edge of the capacitor bottom electrode is preferably formed having either a slanted shape or a rounded shape. The bit line may be formed within the interlayer insulating layer.
According to the other aspect of the present invention, a method for manufacturing the DRAM cell capacitor includes the steps of forming a field oxide layer over a semiconductor substrate to define active and inactive regions, forming a pad electrode over the active region, forming an interlayer insulating layer over the pad electrode and the field oxide layer, forming a contact hole in the interlayer insulating layer to expose the pad electrode, forming a conductive layer over interlayer insulating layer and filling up the contact hole, forming a photoresist pattern over the conductive layer to define a capacitor bottom electrode, simultaneously etching an upper portion of the conductive layer using the photoresist pattern as a mask, and forming a polymer on sidewalls of the photoresist pattern to etch the upper portion of the conductive layer and to thereby angle a top edge of the conductive layer, etching a remaining portion of the conductive layer using a combination of the photoresist pattern and the polymer as a mask until an upper surface of the interlayer insulating layer is exposed, to thereby form the capacitor bottom electrode having a top surface, one or more sidewalls, and the top edge formed between the top surface and the one or more sidewalls, removing the photoresist pattern and the polymer, forming an HSG silicon layer on the capacitor bottom electrode in order that the capacitor bottom electrode has a rugged surface, wherein the HSG silicon layer is formed only on the top surface and the one or more sidewalls of the capacitor bottom electrode, forming a capacitor dielectric layer over the capacitor bottom electrode, and forming a capacitor top electrode over the capacitor dielectric layer.
The top edge of the conductive layer is preferably formed to have either a slated shape or a rounded shape. The conductive layer preferably has a thickness of about 9000 Å, and the upper portion of the conductive layer has a thickness in the range of 50 Å to 200 Å. The step of etching the upper portion of the conductive layer preferably uses a mixture of CHF
3
and Ar gases as an enchant, while the step of etching the remaining portion of the conductive layer preferably uses a material selected from a group consisting of a mixture of Cl
2
, SF
6
, and N
2
gases, and a mixture of HBr and Cl
2
gases.
The method may further comprise the steps of etching an upper portion of the interlayer insulating layer so as to expose a lower surface of the conductive layer, and washing the semiconductor substrate. The step of etching the upper portion of the interlayer insulating layer may use a washing liquid that includes a mixture of NH
4
F and HF, and a mixture of NH
3
, H
2
O
2
,
Han Min-seog
Lee Hyung-Seok
Nam Seok Woo
Shin Ji-Chul
Jones Volentine, L.L.C.
Loke Steven
Samsung Electronics Co,. Ltd.
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