DRAM cell capacitor and manufacturing method thereof

Details DRAM cell capacitor and manufacturing method thereof DRAM cell capacitor and manufacturing method thereof

2002-09-04

2003-12-30

Trinh, Michael (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S306000, C257S309000, C257S379000, C257S532000

Reexamination Certificate

active

06670663

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. More specifically, the present invention is directed to a dynamic random access memory (DRAM) cell capacitor.
2. Description of Background Art
For more than three decades, there has been a steady miniaturization of device dimensions being used for integrated circuit technology. As the chip density of memory cells increase, the area available for a capacitor of a DRAM storage cell (i.e., storage node) shrinks.
A relatively large capacitance is required for a high signal-to-noise ratio in a sense amplifier, and for the reduction of the soft errors due to alpha particle interference. Therefore there is a desire to reduce the cell dimension and yet retain a high capacitance, thereby achieving both high cell integration and reliable operation.
For example, it is known in the semiconductor manufacturing industry that the capacitance of a cell capacitor, even in the gigabit storage range, should be at least 30 femto-farad. One approach for increasing the capacitance while maintaining high-density integration of the storage cells is directed toward the shape of the capacitor electrode. In this approach, the polysilicon layer implementing the capacitor electrode can have protrusions, fins, cavities, etc., to increase the capacitance while maintaining the small area occupied on the substrate surface.
For example, Fazan et al., in U.S. Pat. No. 5,278,091, describe a capacitor over bit line (COB) storage node featuring a hemispherical grained (HSG) polysilicon layer on the storage node, which provides increased surface area.
However, as the chip density increases beyond the gigabit range and the minimum feature size approaches the 0.1 :m scale, it is likely that one will observe a bridge problem between the adjacent storage nodes in a DRAM cell capacitor. Since a bridge between the adjacent storage nodes can cause twin-bit and multi-bit failures in the manufacture of high-density DRAMs, it is crucial to resolve the bridge phenomena before the implementation of a stacked capacitor. In the case of a “box-type” stacked capacitor, increasing the distance between the adjacent storage nodes can alleviate the bridge problem. Increasing inter cell distance, however, defeats minimization.
Recently, a capacitor structure named “concave structure” has been proposed in an effort to resolve the above-mentioned bridge problem. The concave structure employs a sacrificial oxide to implement a cylindrical capacitor. A method of manufacturing the concave cylindrical capacitor is disclosed in a technical paper entitled, “A New Planar Stacked Technology (PST) for Scaled and Embedded DRAMs,” by S. P. Sim, et al., published in the Technical Digest of International Electron Device Meeting (IEDM), pp. 597-600, 1996.
FIGS. 1A
to
1
D are schematic cross-sectional views illustrating various manufacturing steps for a traditional concave cell capacitor.
The prior art, as disclosed in
FIGS. 1A-1D
and
2
A-
2
D, shows a method of manufacturing the concave cylindrical capacitor. The manufacturing method comprises providing an activation layer
56
having isolation elements
55
that define active regions
53
; forming a contact pad
58
in electrical connection with active regions
53
; providing an insulating film
54
over the activation layer
56
and the isolating elements
55
; forming storage nodes
52
within insulating film
54
; forming a contact
51
by employing a sacrificial oxide layer
50
; depositing a polysilicon layer
57
over the layered structure, for serving as a storage node; filling the contact hole
51
with a protective oxide
59
; performing a chemical mechanical polishing (CMP) process for cell isolation and removing the sacrificial oxide layer
50
and the protection oxide
59
.
The manufactured device disclosed in the prior art, however, still suffers from a “lift-off” problem of the polysilicon layer. This is because some residue of the polysilicon layer is left on the surface of the wafer after the CMP process.
FIGS. 2A and 2B
are schematic cross-sectional views illustrating the “lift-off” problem of the polysilicon layer as it occurs in the prior art.
Referring to
FIGS. 2A and 2B
, some residue
60
of the polysilicon layer
57
is left on the surface of the sacrificial oxide layer
50
if the contact hole
51
is not completely open. This is called “NOT OPEN” in the art due to the close spacing between the adjacent storage nodes
52
.
Furthermore, some polysilicon patches
60
may detach from the polysilicon layer
57
and float during the CMP process. This can cause failure of the semiconductor device if the polysilicon layer sticks to the surface of the wafer. In addition, an alignment key may not be completely opened if the step height is relatively high, thereby causing similar “NOT OPEN” problems to be observed during the step of forming a buried contact.
In this case, the floating patches
60
or the residues of the patterned polysilicon can stick to the surface of the cell area, which consequently causes failure in the manufacture of a DRAM cell capacitor.
SUMMARY OF THE INVENTION
There is a need in the art for a cell capacitor that is not subjected to the limitations of the prior art.
Accordingly, it is a feature of the present invention to provide a cell capacitor for the manufacture of a DRAM.
Another feature of the present invention is to provide a method of manufacturing a cell capacitor, which resolves the “lift-off” problem of the polysilicon patches of the prior art.
Still another feature of the present invention is to provide a cell capacitor and a manufacturing method thereof, which resolve the “NOT OPEN” problem of the prior art.
Still yet another feature of the present invention is to provide a cell capacitor and a manufacturing method thereof, which cures the floating problem of polysilicon patches, which detaches from the sacrificial oxide layer.
A further feature of the present invention is to provide a cell capacitor and a manufacturing method of the same, which reduces the number of lithographic stages.
Yet another feature of the present invention is to provide a cell capacitor and a manufacturing method thereof, which prevents the misalignment between a storage node and a node contact.
As a result, it becomes possible to implement a concave cell capacitor having neither the “bridge” nor the “lift-off” problems of the prior art.
In accordance with a broad aspect of the present invention, provided is a method of manufacturing a cylindrical cell capacitor comprising forming a first insulating layer over a substrate, forming a first conductive layer on the first insulating layer, forming a first opening window to expose a portion of the first insulating layer by etching the first conductive layer, providing a first dielectric layer on at least an inner surface of the first opening window, forming a second conductive layer on the first dielectric layer, providing a spacer on sidewalls of the first opening window by etching the second conductive layer and first dielectric layer, forming a second opening window by etching the first insulating layer using the spacer as a mask, and forming a third conductive layer in at least the first and second opening windows to electrically connect with the substrate. Preferably, the step of forming the first opening window comprises forming a contact opening by selectively etching a portion of the second insulating layer and etching the first conductive layer using the contact opening as a mask.
The present invention further provides a method of manufacturing a cell capacitor wherein the lower electrode pattern and the lower electrode contact are simultaneously fabricated by a single photolithography step. According to an alternate embodiment of the present invention, the upper electrode of the cell capacitor is formed prior to the fabrication of the lower electrode.
In the manufacture of a cell capacitor in accordance with the present invention, a transistor havin

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