DRAM cell array and memory cell arrangement having vertical...

Details DRAM cell array and memory cell arrangement having vertical... DRAM cell array and memory cell arrangement having vertical...

2006-11-28

2006-11-28

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S243000

Reexamination Certificate

active

07141845

ABSTRACT:
Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

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IBM Corp., “High Density Cross-Point Cell in an Interleaved Sense Amplifier Layout,” IBM Technical Disclosure Bulletin, vol. 30, No. 5, pp. 406-408, (Oct. 1987).

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