DRAM cell arrangement with vertical MOS transistors, and...

Details DRAM cell arrangement with vertical MOS transistors, and... DRAM cell arrangement with vertical MOS transistors, and...

2005-09-06

2005-09-06

Nelms, David (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C257S329000

Reexamination Certificate

active

06939763

ABSTRACT:
DRAM cell arrangement with vertical MOS transistors, and method for its fabrication. Channel regions arranged along one of the columns of a memory cell matrix are parts of a rib which is surrounded by a gate dielectric layer. Gate electrodes of the MOS transistors belonging to one row are parts of a strip-like word line, so that at each crossing point of the memory cell matrix there is a vertical dual-gate MOS transistor with gate electrodes of the associated word line formed in the trenches on both sides of the associated rib.

REFERENCES:
patent: 5888864 (1999-03-01), Koh et al.
patent: 6326269 (2001-12-01), Jeng et al.
patent: 6800898 (2004-10-01), Cappelani et al.
patent: 5-29573 (1993-02-01), None
patent: 00/55905 (2000-09-01), None
International Search Report, dated Aug. 13, 2003 for PCT/EP02/05651.
International Preliminary Examination Report, dated Oct. 21, 2003 for PCT/EP02/05651.

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