DRAM cell arrangement and method for the production thereof

Details DRAM cell arrangement and method for the production thereof DRAM cell arrangement and method for the production thereof

1998-11-13

1999-11-02

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, 257301, 257302, 257306, 257401, H01L 2972

Patent

active

059775890

ABSTRACT:
A memory cell containing at least three vertical transistors. A first transistor and a second transistor, or a third transistor are arranged over each other with reference to a y-axis proceeding perpendicularly to a surface of a substrate. The second transistor and the third transistor can be arranged at opposite sides of a semiconductor structure, while the first transistor is arranged at both sides. Source/drain regions of the transistors can overlap.

REFERENCES:
patent: 5872374 (1999-02-01), Tang et al.
Heshami et al, IEEE J. of Solid-State Circuits, vol. 31, No. 3, Mar. 1996, pp. 376-383.

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