Dram cell and space-optimized memory array

Details Dram cell and space-optimized memory array Dram cell and space-optimized memory array

2005-04-05

2005-04-05

Tran, Minhloan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S301000, C257S328000, C257S329000, C257S334000

Reexamination Certificate

active

06876025

ABSTRACT:
The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. As a result, a conductive channel can be formed within the channel region depending on the potential of the word line. Preferably, the extent of the trench hole in the word line direction is at least 1.5 times as large as in the bit line direction.

REFERENCES:
patent: 6410391 (2002-06-01), Zelsacher
patent: 6448600 (2002-09-01), Schlösser et al.
patent: 6521935 (2003-02-01), Krautschneider et al.
patent: 20030062555 (2003-04-01), Miyai et al.
patent: 20030169629 (2003-09-01), Goebel et al.
patent: 199 54 867 (2000-12-01), None

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