DRAM capacitor process

Details DRAM capacitor process DRAM capacitor process

1997-03-11

1999-11-23

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438397, H01L 218242

Patent

active

059899565

ABSTRACT:
A DRAM capacitor is formed by providing an opening to the surface of the drain of a memory cell's pass transistor. A first layer of polysilicon is deposited over the device and in contact with the drain of the pass transistor. Arsenic ions are implanted into the first layer of polysilicon and the first layer of polysilicon is annealed. A second layer of polysilicon is deposited over the first. Phosphorus ions are implanted into the surface of the second layer of polysilicon. A mask is formed over the two polysilicon layers, and the two layers are etched to define the lateral extent of the memory cell capacitor's lower electrode. An etch that preferentially etches doped polysilicon is used to laterally etch the (doped and annealed) first polysilicon layer, thereby undercutting the second polysilicon layer. The second polysilicon layer is then annealed. A dielectric film is formed on the surface of the lower electrode and an upper electrode consisting of doped polysilicon is formed over the surface of the dielectric layer. Forming a DRAM capacitor in this manner prevents impurities implanted into the polysilicon lower electrode of the capacitor from diffusing into the substrate in a manner which could expand the size of the drain region.

REFERENCES:
patent: 5286668 (1994-02-01), Chou
patent: 5789291 (1998-08-01), Sung

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