DRAM capacitor including Cu plug and Ta barrier and method...

Details DRAM capacitor including Cu plug and Ta barrier and method... DRAM capacitor including Cu plug and Ta barrier and method...

1999-06-25

2001-01-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S254000, C438S003000, C438S396000, C438S397000, C257S306000, C257S310000, C257S532000, C257S534000

Utility Patent

active

06168991

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
Not Applicable
FIELD OF THE INVENTION
This invention relates to dynamic random access memory (DRAM) used in semiconductors. More specifically, the invention relates to a method of constructing a capacitor of a dynamic random access memory cell.
BACKGROUND OF THE INVENTION
In order to satisfy demands for high density DRAM semiconductor chips, microminiaturization employing sub-micron features are employed. However, to achieve high DRAM densities at low costs, new designs and technology integration are needed. Typically, a DRAM storage cell comprises a transistor and a capacitor wherein the gate of the transistor is controlled by a word line signal, and data represented by the logic level of the storage capacitor is written into or read out of the capacitor through a bit line signal.
One recent design and fabrication process teaches a DRAM cell structure and method of manufacture. The DRAM cell structure is produced by vertically aligning a polysilicon word line structure, to an underlying bit line structure, and to any overlying capacitor structure. Still other methods for fabricating DRAM capacitors and DRAM cells are known in the art, but these methods for achieving sub-micron features, such as stacked/trench capacitors for DRAM cells, are believed to be overly complicated. Furthermore, the prior art does not show a capacitor for a DRAM cell that uses copper. Copper is now being used to facilitate the further microminiaturization of sub-micron features.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a capacitor for a DRAM cell and method of manufacture with the capacitor having a high capacitance to maintain a high signal to noise ratio in reading the memory cell and to reduce “soft” errors (due to alpha particle interference).
It is another object of the invention to provide a cost effective method of manufacture which produces a capacitor for a DRAM cell having a small feature size.
It is yet another object of the invention to provide a capacitor for a DRAM cell which uses films having a higher dielectric constant to reduce the size of the capacitor without reducing total capacitance.
It is a further object of the invention to provide a cost effective method of manufacture requiring a minimum number of processing steps and mask registrations for the formation of the DRAM capacitor.
It is still another object of the invention is to provide a method of manufacture which reduces the number of masks used in processing and/or device size in an integrated logic-memory chip where processing for logic and memory are compatible.
These and other objects of the invention are achieved by a capacitor for a DRAM cell comprising a first electrode layer, a second electrode layer, and a dielectric film. The capacitor is disposed in a first opening defined in a second dielectric layer and overlaying a first plug through a first dielectric layer. The first plug is electrically connected to a transistor. The first electrode layer is electrically connected to the first plug. The second electrode layer can act as a barrier between a second plug exposed by a second opening and the second opening.
The first and second electrode layer can be formed from Ta and TaN, and the dielectric film can be formed from tantalum oxide. A plug layer electrically connected to the second electrode layer can also be included. The plug layer can be formed from copper.
An additional embodiment of the invention discloses a method for forming a capacitor in a DRAM cell. The DRAM cell comprises a transistor and first and second plugs through the first dielectric layer. The first and second dielectric layers are disposed over the transistor, and the first and second plugs electrically connected to the transistor. The method comprises the steps of: forming a first opening in the second dielectric layer exposing a portion of the first plug; depositing a first electrode layer on exposed surfaces of the first opening and the first plug; depositing a dielectric film over the first electrode layer; and depositing a second electrode layer over the dielectric film thereby forming a capacitor structure in the first opening.
The method can also include the step of forming a second opening in the second dielectric layer after depositing the high dielectric film. The second opening exposes the second plug, and the deposition of the second electrode layer forms a barrier layer between the second opening and the second plug. Also, the first and second openings can be filled with a plug layer, for example copper.
Advantageously, the DRAM capacitor of a DRAM cell having a metal-oxide-semiconductor field effect transistor (MOSFET) which requires only one additional mask subsequent to formation of the MOSFET. The MOSFET is conventionally formed in and on a semiconductor substrate and the storage capacitor is formed in a trench provided in a top dielectric of the transistor, rather than in the adjoining silicon, thus utilizing less substrate surface area. The method of the invention can reduce the DRAM cell to about 0.5 square microns in a technique which is compatible with forming both the memory and the processing devices on a single integrated substrate.


REFERENCES:
patent: 5895239 (1999-04-01), Jeng et al.
patent: 6010927 (1999-04-01), Jones, Jr. et al.

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