Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2006-08-31
2008-11-18
Dinh, Son (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S189070, C365S189090
Reexamination Certificate
active
07453748
ABSTRACT:
A DRAM bit line precharge voltage generator comprises a first amplifier having a first current source and comparing a first voltage with a precharge voltage to control a first PMOS transistor, a second amplifier having a second current source and comparing a second voltage with the precharge voltage to control a second PMOS transistor, a third amplifier having a third current source and comparing a third voltage with the precharge voltage to control a first NMOS transistor, and a fourth amplifier having a fourth current source and comparing the first voltage with the precharge voltage to control a second NMOS transistor. The precharge voltage feedbacks from an output node connected between the second PMOS transistor and the first NMOS transistor. The DRAM bit line precharge voltage generator with a low-frequency pole provided by the first amplifier, the first PMOS transistor, the fourth amplifier, and the second NMOS transistor exhibits the characteristics of robustness, low standby current and low-output impedance.
REFERENCES:
patent: 5255232 (1993-10-01), Foss et al.
patent: 6265858 (2001-07-01), Park
patent: 6559707 (2003-05-01), Hwang
patent: 6687166 (2004-02-01), Takahashi et al.
patent: 6687639 (2004-02-01), Taniguchi et al.
Dinh Son
Elite Semiconductor Memory Technology Inc.
Oliff & Berridg,e PLC
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