Drain voltage pump circuit for nonvolatile memory device

Details Drain voltage pump circuit for nonvolatile memory device Drain voltage pump circuit for nonvolatile memory device

1997-03-05

1998-10-06

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518909, 365226, 327536, G11C 700

Patent

active

058187669

ABSTRACT:
A program drain voltage pump is provided that employs multiple pumping sections that are adaptively controlled to provide a pumped drain voltage (VD) that rises smoothly and rapidly to an optimum VD level for programming EPROM or flash memory cells and maintains VD at the optimum level with minimal ripple. The pumping sections are configured to pump a common VD node that is coupled to the drains of the EPROM or flash memory cells. Each pumping section is driven by a clock signal whose pulses are out of phase with the clock signals driving the other pumping sections. All of the clock signals have roughly the same frequency. Due to the staggered clocks, each pump is activated during a different respective time period, which smooths out VD. Additionally, to provide an even faster and smoother pumped VD than with multiphase clocking alone, an embedded controller is provided that adaptively adjusts the frequency and slew rate of the various clock pulses throughout the pumping operation, which alters the amount by which VD is raised for a given clock pulse.

REFERENCES:
patent: 5367489 (1994-11-01), Park et al.
patent: 5528538 (1996-06-01), Sakuta et al.
patent: 5546296 (1996-08-01), Savignac et al.
patent: 5561385 (1996-10-01), Choi

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