Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-09-25
2004-07-06
Auduong, Gene (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230080, C365S193000
Reexamination Certificate
active
06760261
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to a circuit and method for suppressing noise of a postamble data strobe signal (DQS) in a double data rate (DDR) synchronous dynamic random access memory (SDRAM).
2. Description of the Related Art
Synchronous dynamic random access memories (hereinafter, referred to as SDRAMs) have been developed for achieving a high speed of operation in DRAM devices. The SDRAM operates in synchronization with an external clock signal and includes a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM and the like.
The SDR SDRAM operates in synchronization with rising edges of the external clock, so that one data is processed within one period of the external clock. On the contrary, the DDR SDRAM operates in synchronization with rising and falling edges of a data strobe signal (DQS), so that two successive data are processed within one period of the external clock. Therefore, compared with the SDR SDRAM, the DDR SDRAM achieves at least twice the operation speed without increasing a frequency of the external clock.
FIG.
1
(
a
) is a timing diagram illustrating an operation of a conventional DDR SDRAM. In DDR SDRAMs, data arrives centered to both edges of the DQS signal, i.e., a rising edge and a falling edge. The DQS signal can advance or trail a clock signal (VCLK), generated by an external clock, by up to +/−25% of the cycle time, i.e., tDQSSmin and tDQSSmax respectively. After the initial latching, the data is divided on separate data lines (SRWD) which direct the data further into a memory array according to the edge of the DQS signal they were originally centered to (even/odd data). With the falling edge of the DQS signal, the data is driven onto those separate data lines (SRWD). The data is driven into the memory array after being internally latched with the rising edge of a signal derived from a CAS (Column Address Strobe) signal (see Latchpoint in FIG.
1
). This CAS signal is ignorant to the tDQSS value (a cycle period of the DQS signal). After the last valid DQS pulse, the DQS signal is not driven anymore and the system termination pulls the DQS signal into a tristate level, as shown in FIG.
1
(
a
) at point A.
After the last valid DQS edge, an off-chip driver driving the DQS signal stops driving and the DQS signal is pulled from a postamble state, which is defined as a low DQS signal before data issues, into the tristate level. At this point, the DQS line is subject to noise from outside the chip or memory device, e.g., switching noise, ringing, etc. Referring to FIG.
1
(
b
), in the case of tDQSSmin (Early DQS signal), noise on the DQS line can cause a false falling edge, possibly forcing invalid data (iDATA) onto the separate data lines (SRWDea) before the correct data can be latched with the rising edge of the CAS signal (see point B in FIG.
1
(
b
)). Additionally, in the case of tDQSSmax (Late DQS signal) as shown in FIG.
1
(
c
), noise can possibly force invalid data (iDATA) onto the separate data lines at point C, however, this will not effect the integrity of the data stored in the memory device since it occurs after the rising edge of the CAS signal and will not be latched into the memory array.
SUMMARY OF THE INVENTION
Accordingly, it is an aspect of the present invention to provide a circuit and method for storing data in a memory device which prevents noise from latching invalid data into a memory array of the memory device.
It is another aspect of the present invention to provide a circuit and method for storing data in a memory device which forces a data strobe signal to have a minimum pulse width effectively eliminating invalid data latched by unwanted noise.
According to one aspect of the present invention, a circuit for storing data in a memory device is provided including a data input latch circuit for receiving data to be stored and for latching the data in a memory array in response to a control signal; and a control signal generator for generating the control signal in response to a data strobe signal wherein the control signal has a predetermined minimum pulse width of the data strobe signal.
According to another aspect of the present invention, the control signal generator includes a reset/set flip-flop for generating the control signal, wherein the flip-flop is set by the data strobe signal; and a low pass filter for receiving the data strobe signal and for outputting a reset signal to the flip-flop if the data strobe signal is greater than the predetermined minimum pulse width. The control signal generator further includes a delay element coupled between the low pass filter and the flip-flop for delaying the resetting of the flip-flop for a period greater than the predetermined minimum pulse width.
In another aspect of the present invention, a method for storing data in a memory device includes the steps of receiving data on a data bus; latching the data from the data bus in response to a data strobe signal; and latching the data into a memory array in response to a control signal wherein the control signal has a predetermined minimum pulse width of the data strobe signal.
REFERENCES:
patent: 4608669 (1986-08-01), Klara et al.
patent: 5309035 (1994-05-01), Watson, Jr. et al.
patent: 6275441 (2001-08-01), Oh
patent: 6552957 (2003-04-01), Yagishita
patent: 2001/0039602 (2001-11-01), Kanda et al.
Alexander George William
Partsch Torsten
Auduong Gene
Infineon - Technologies AG
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