Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – Reverse-biased pn junction guard region
Reexamination Certificate
1999-07-21
2001-04-10
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
Reverse-biased pn junction guard region
C257S490000, C257S495000, C257S341000
Reexamination Certificate
active
06215168
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to silicon power semiconductor devices and, more particularly, to a device having improved edge passivation.
BACKGROUND OF THE INVENTION
Protection of device edges, where the region of the device makes the transition from its internal structure to its external structure, is an essential aspect of the design of high voltage semiconductor devices such as MOSFETs, IGBTs, MCTs, bipolar transistors, thyristors, and diodes. The edge protection, or edge passivation structure, must perform the function of distributing the applied voltage over a wider region on the surface of the device than it occupies within the silicon substrate, thereby ensuring that the electric field at the surface is low enough to prevent arcing outside the silicon substrate or avalanche breakdown within the substrate near its surface.
In producing a P-N junction diode by a typical planar diffusion technique, a cylindrical junction is formed by diff-using a dopant through an oxide window. Because of the curvature at the edge of the junction, it produces a greater electric field than an ideal planar junction. As a result, the breakdown voltage of a cylindrical junction diode is substantially lower than an ideal planar junction diode.
Junction termination extension (JTE) is an edge passivation technique for reducing the concentration of the electric field in a cylindrical junction diode. To support the applied voltage at the surface, a JTE region is characterized by a dopant charge per unit area sufficiently low to allow the field to spread all the way, or most of the way, through the region prior to the onset of avalanche breakdown. The optimum dopant density per unit area for such a region is of the order of 1×10
12
to 1×10
13
per square centimeter, which approximates the maximum charge per unit area that a JTE region can contain prior to the onset of avalanche breakdown. Too low a density will allow the region to deplete at a field too low to support adequate voltage; too high a density will cause the depletion region to be too thin to support adequate voltage. JTE is described in, for example, V. A. K. Temple, “Junction termination extension, a new technique for increasing avalanche breakdown voltage and controlling surface electric field in p-n junction,” IEEE
International Electron Devices Meeting Digest
. 1977, Abstract 20.4, pp 423-426, the disclosure of which is incorporated herein by reference.
U.S. Pat. No. 5,712,502 to Mitlehner et al., the disclosure of which is incorporated herein by reference, describes a semiconductor device that includes an active area, a depletion zone whose vertical extension is at a maximum beneath the active area, and a junction termination whose lateral extension is greater than the maximum vertical extension of the depletion zone.
U.S. Pat. No. 4,927,772 to Arthur et al., the disclosure of which is incorporated herein by reference, describes a method of making a high voltage semiconductor device using two masks that enable the formation of a graded multiple-zone JTE region and a graded multiple zone P+ region.
U.S. Pat. No. 4,667,393 to Ferla et al., the disclosure of which is incorporated herein by reference, describes a method for making a high voltage semiconductor device having a stepped continuous JTE zone formed by implanting and diffusing decreasing concentrations of a dopant through a series of mask apertures prior to forming emitter and channel stop regions and metal emitter, base, and collector contacts.
U.S. Pat. No. 4,648,174 to Temple et al., the disclosure of which is incorporated herein by reference, describes a process of forming a semiconductor that includes a multiplezone junction termination region adjacent a reverse-blocking junction.
FIGS. 1
,
2
, and
3
schematically illustrate several known JTE structures. In
FIG. 1
, the dopant density in the JTE region is depicted as constant, and in
FIG. 2
it is shown as decreasing in discrete steps with increasing distance from the active region. The JTE structure of
FIG. 3
is similar to that of
FIG. 2
, except that the dopant density decreases in a smooth gradient. A stepped or graded density, as shown in
FIGS. 2 and 3
, is more tolerant of variations in dopant density than the constant-density situation of FIG.
1
.
Finding an improved way to reduce the electric field at the active area-JTE junction of a power semiconductor device and thereby increase its breakdown volta e remains a highly desirable goal, one that is realized in the present invention.
SUMMARY OF THE INVENTION
The present invention is directed to a silicon semiconductor die that comprises a heavily doped silicon substrate and an upper layer comprising doped silicon of a first conductivity type disposed on the substrate. The upper layer includes an active region that comprises a well region of a second, opposite conductivity type and an edge passivation zone comprising a junction termination extension (JTE) JTE region that ji includes portions extending away from and extending beneath the well region. The JTE region is of varying dopant density, the dopant density being maximum at a point sub. tantially directly beneath the junction at the upper surface of the upper layer of the JTE region with the well region. The dopant density of the JTE region decreases in both lateral directions from its maximum point, lessening in both the portions extending away from and beneath the well region.
REFERENCES:
patent: 4648174 (1987-03-01), Temple et al.
patent: 4667393 (1987-05-01), Ferla et al.
patent: 4927772 (1990-05-01), Arthur et al.
patent: 5712502 (1998-01-01), Mitlehner et al.
Brush Linda Susan
Neilson John Mannine Savidge
Intersil Corporation
Jaeckle Fleischmann & Mugel LLP
Loke Steven
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