Double-sided thermally enhanced IC chip package

Details Double-sided thermally enhanced IC chip package Double-sided thermally enhanced IC chip package

2005-02-01

2005-02-01

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With heat sink means

C257S777000

Reexamination Certificate

active

06849932

ABSTRACT:
The present invention is to provide a double-sided thermally enhanced IC chip package which includes a chip being received in an opening of a substrate and electrically connected to a conductive circuit pattern on a top surface of the substrate through bonding wires. A thermally and electrically conductive planar member is attached to an inactive side of the chip through a thermally and electrically conductive adhesive layer. A portion of an active side of the chip to which the bonding wires are connected is encapsulated by a dielectric encapsulant, and the other portion of the active side of the chip is covered by a thermally and electrically conductive encapsulant. Thus, heat generated by the chip can be efficiently dissipated through the planar member and the thermally and electrically conductive encapsulant. The present invention also discloses a stacked chip package with double-sided heat dissipation capability.

REFERENCES:
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patent: 5801432 (1998-09-01), Rostoker et al.
patent: 6127724 (2000-10-01), DiStefano
patent: 6380615 (2002-04-01), Park et al.
patent: 6507102 (2003-01-01), Juskey et al.
patent: 6614660 (2003-09-01), Bai et al.
patent: 6713856 (2004-03-01), Tsai et al.

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