Double-sided etching method using embedded alignment mark

Details Double-sided etching method using embedded alignment mark Double-sided etching method using embedded alignment mark

2006-09-28

2008-08-19

Deo, Duy-Vu N (Department: 1792)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Physical stress responsive

C438S051000, C438S052000, C438S053000, C438S054000, C257S619000

Reexamination Certificate

active

07413920

ABSTRACT:
A double-sided etching method using an embedded alignment mark includes: preparing a substrate having first and second alignment marks embedded in an intermediate portion thereof; etching an upper portion of the substrate so as to expose the first alignment mark from a first surface of the substrate; etching the upper portion of the substrate using the exposed first alignment mark; etching a lower portion of the substrate so as to expose the second alignment mark from a second surface of the substrate; and etching the lower portion of the substrate using the exposed second alignment mark.

REFERENCES:
patent: 6020215 (2000-02-01), Yagi et al.
patent: 2006/0057755 (2006-03-01), Weber
patent: 2006/0205106 (2006-09-01), Fukuda et al.
patent: 2007/0128757 (2007-06-01), Ko et al.
patent: 10-2006-0034790 (2006-04-01), None

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