Double pass transistor logic with vertical gate transistors

Details Double pass transistor logic with vertical gate transistors Double pass transistor logic with vertical gate transistors

2000-08-29

2002-04-30

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S119000, C326S113000, C326S101000

Reexamination Certificate

active

06380765

ABSTRACT:

CROSS REFERENCE TO RELATED CO-PENDING AND CO-FILED APPLICATIONS
This application is related to the following co-pending, commonly assigned U.S. patent applications: entitled “Static Pass Transistor Logic with Transistors with Multiple Vertical Gates,” Ser. No. 09/580,901; and “Vertical Gate Transistors in Pass Transistor Logic Decode Circuits,” Ser. No. 09/580,860, both filed on May 30, 2000 and which disclosures are herein incorporated by reference. This application is further related to the following co-pending, commonly assigned U.S. patent application: “Vertical Gate Transistors in Pass Transistor Programmable Logic Arrays,” Ser. No. 09/643,296, which is filed on even date herewith and also incorporated herein by reference.
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to integrated circuits and in particular to double pass transistor logic with vertical gate transistors.
BACKGROUND OF THE INVENTION
Many integrated circuits include multiple transistors arrayed such that a combination of activated transistors produce a logical function. Such transistors in the array are activated, in the case of MOSFET devices, by either applying or not applying a potential to the gate of the MOSFET. This action either turns on the transistor or turns off the transistor. Conventionally, each logical input to the integrated circuit is applied to an independent MOSFET gate. Thus, according to the prior art, a full MOSFET is required for each input to the integrated circuit. Requiring a full MOSFET for each logic input consumes a significant amount of chip surface area. Conventionally, the size of each full MOSFET, e.g. the space it occupies, is determined by the minimum lithographic feature dimension. Thus, the number of logical functions that can be performed by a given integrated circuit is dependent upon the number of logical inputs which is, in turn, dependent upon the available space to in which to fabricate an independent MOSFET for each logic input. In other words, the minimum lithographic feature size and available surface determine the functionality limits of the programmable logic array.
Pass transistor logic is one of the oldest logic techniques and has been described and used in NMOS technology long before the advent of the CMOS technology currently employed in integrated circuits. A representative article by L. A. Glasser and D. W. Dobberpuhl, entitled “The design and analysis of VLSI circuits,” Addison-Wesley, Reading, Mass., 1985, pp. 16-20, describes the same. Pass transistor logic was later described for use in complementary pass transistor circuits in CMOS technology. Articles which outline such use include articles by J. M. Rabaey, entitled “Digital Integrated Circuits; A design perspective,” Prentice Hall, Upper Saddle River, N.J., pp. 210-222, 1996, and an article by K. Bernstein et al., entitled “High-speed design styles leverage IBM technology prowess,” MicroNews, vol. 4, no. 3, 1998. What more, there have been a number of recent applications of complementary pass transistor logic in microprocessors. Articles which describe such applications include articles by T. Fuse et al., entitled “A 0.5V 200 mhz 1-stage 32b ALU using body bias controlled SOI pass-gate logic,” Dig. IEEE Int. Solid-State Circuits Conf., San Francisco, pp. 286-287, 1997, an article by K. Yano et al., entitled “Top-down pass-transistor logic design,” IEEE J. Solid-State Circuits, Vol. 31, no. 6, pp. 792-803, June 1996, and an article by K. H. Cheng et al., entitled “A 1.2V CMOS multiplier using low-power current-sensing complementary pass-transistor logic”, Proc. Third Int. Conf. On Electronics, Circuits and Systems, Rodos, Greece, 13-16 Oct., vol. 2, pp. 1037-40, 1996.
In another approach, double pass transistor logic has been developed to overcome concerns about low noise margins in pass transistor logic. This has been described in an article by S. I. Kayed et al., entitled “CMOS differential pass-transistor logic (CMOS DPTL) predischarge buffer design,” 13th National Radio Science Conf., Cairo, Egypt, pp. 527-34, 1996, as well as in an article by V. G. Oklobdzija, entitled “Differential and pass-transistor CMOS logic for high performance systems,” Microelectronic J., vol. 29, no. 10, pp. 679-688, 1998. Combinations of pass-transistor and CMOS logic have also been described. S. Yamashita et al., “Pass-transistor CMOS collaborated logic: the best of both worlds,” Dig. Symp. On VLSI Circuits, Kyoto, Japan, June 12-14, pp. 31-32, 1997. Also, a number of comparisons of pass transistor logic and standard CMOS logic have been made for a variety of different applications and power supply voltages. These studies are described in an article by R. Zimmerman et al., entitled “Low-power logic styles: CMOS versus pass transistor logic,” IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1790, July 1997, and in an article by C. Tretz et al., “Performance comparison of differential static CMOS circuit topologies in SOI technology,” Proc. IEEE Int. SOI Conference, October 5-8, FL, pp. 123-4, 1998.
Thus, static pass transistor CMOS logic circuits, as shown in
FIG. 5A
, have been used in CMOS technology and integrated circuits. The main problem with static pass transistor logic circuits is the threshold voltage drop at the input across a pass transistor. If as shown in
FIG. 5A
the input is high at VDD then if the pass transistor is a normal enhancement mode device the input voltage will rise only to VDD−VTN, where VTN is the threshold voltage of the NMOS transistor. Worse still, it will, in theory, take an infinite amount of time to reach this voltage since the NMOS pass transistor has a final state which has infinite resistance. If, as shown in
FIG. 5B
, the output of one pass transistor is used to drive the gate of another transistor then the capacitor at the input to the inverter will charge only to VDD−2 VTN. This is, in particular, unacceptable in low power supply circuits and this possibility must be precluded by design rules.
Various techniques have been used to overcome some of the threshold voltage drop problem. One is the use of level restore circuits. The level restore circuits such as shown in FIG.
6
A and
FIG. 6B
are essentially equivalent. If the inverter input is switching high then the output is going low, this low output is used in a feedback circuit to drive the gate of the extra PMOS device low and pull the input up. This is a positive feedback circuit which tends to latch the input high regardless of how slowly the original input signal was rising. In this manner the level restore circuits overcome the threshold voltage drop at the input in pass transistor logic circuits.
Another technique is the development of differential pass transistor logic, as shown in
FIGS. 7A and 8A
. In differential pass transistor logic both NMOS and PMOS transistors are used as pass transistors and the threshold voltage drop does not occur, one of these transistor is always on in a high conductivity state.
FIGS. 9A and 9B
illustrate conventional application of differential pass transistor logic in the form of an XOR logic gate and a one bit full adder, sum circuit, respectively.
However, all of these studies and articles on pass transistor logic have not provided a solution to the constraints placed on programmable logic arrays by the limits of the minimum lithographic feature size and the deficit in the available chip surface space in combination with the threshold voltage drop issue.
An approach which touches upon overcoming the limits of the minimum lithographic feature size and the deficit in the available chip surface space, is disclosed in the following co-pending, commonly assigned U.S. patent applications by Len Forbes and Kie Y. Ahn, entitled: “Programmable Logic Arrays with Transistors with Vertical Gates,” Ser. No. 09/583,584, “Horizontal Memory Devices with Vertical Gates,” Ser. No. 09/584,566, and “Programmable Memory Decode Circuits with Vertical Gates,” Ser. No. 09/584,564. Those disclosures are all directed toward a non volatile memory cell structure having

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