Double gated vertical transistor with different first and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S329000, C257S331000, C257S332000

Reexamination Certificate

active

06960806

ABSTRACT:
Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

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patent: 5032529 (1991-07-01), Beitman et al.
patent: 5899710 (1999-05-01), Mukai
patent: 6197672 (2001-03-01), Lin et al.
patent: 0 694 977 (1996-01-01), None
Kim K et al, “Double-Gate CMOS: Symmetrical-Versus Asymmetrical-Gate Devices”, IEEE Transactions on Electron Devices, IEEE Inc. New York, US, vol. 48, No. 2, Feb. 2001, pp. 294-299, XP001038978, ISSN: 0018-9383.

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