Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-10-30
2007-10-30
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000
Reexamination Certificate
active
11316307
ABSTRACT:
Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor includes forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.
REFERENCES:
patent: 6413802 (2002-07-01), Hu et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6706571 (2004-03-01), Yu et al.
patent: 6770516 (2004-08-01), Wu et al.
patent: 6798017 (2004-09-01), Leas et al.
patent: 6838322 (2005-01-01), Pham et al.
patent: 6858478 (2005-02-01), Chau et al.
patent: 6867450 (2005-03-01), Kito et al.
patent: 6885055 (2005-04-01), Lee
patent: 6956256 (2005-10-01), Forbes
patent: 7015547 (2006-03-01), Hackler, Sr. et al.
patent: 7026688 (2006-04-01), Kim et al.
patent: 7074623 (2006-07-01), Lochtefeld et al.
patent: 7098498 (2006-08-01), Diorio et al.
patent: 7119384 (2006-10-01), Popp et al.
patent: 2004/0217420 (2004-11-01), Yeo et al.
patent: 2005/0029583 (2005-02-01), Popp et al.
patent: 2005/0035415 (2005-02-01), Yeo et al.
patent: 0721221 (1996-07-01), None
patent: 2002-96654 (2002-12-01), None
patent: 2003-26435 (2003-04-01), None
patent: 2003-0065631 (2003-08-01), None
English language Abstract of Korean Patent No. 2002-96654.
English language Abstract of Korean Patent No. 2003-26435.
English language Abstract of Korean Patent No. 2003-0065631.
Kazuya Asano, et al. “A Folded-channel MOSFET for Deep-sub-tenth Micron Era,” 1998 IEEE International Electron Device Meeting Technical Digest, pp. 1032-1034.
Xue-Jue Huang, et al. “Sub 50-nm FinFET” PMOS, 1999 IEEE International Electron Device Meeting Technical Digest, pp. 67-70.
Jin Gyo-young
Makoto Yoshida
Park Dong-gun
Park Tai-su
Youn Jae-Mun
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Soward Ida M.
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