Double gate FET and fabrication process

Details Double gate FET and fabrication process Double gate FET and fabrication process

2011-01-04

2011-01-04

Pizarro, Marcos D. (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S365000, C257S018000, C257S022000, C257S347000, C257S410000, C257S412000, C257SE29264, C438S279000

Reexamination Certificate

active

07863139

ABSTRACT:
A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.

REFERENCES:
patent: 2001/0010380 (2001-08-01), Maeda
patent: 2004/0094758 (2004-05-01), Usuda et al.
patent: 2004/0197969 (2004-10-01), Chen et al.

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