Double edge triggered flip-flop circuit

Details Double edge triggered flip-flop circuit Double edge triggered flip-flop circuit

2011-08-23

2011-08-23

Le, Vu A (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S154000

Reexamination Certificate

active

08004908

ABSTRACT:
In a double edge triggered flip-flop circuit, a first latch circuit latches input data at either one of rising edge and falling edge of clock signal. A second latch circuit, which is provided in parallel with the first latch circuit, latches the input data at the other of the either one of rising edge and falling edge of the clock signal. At least one of the first latch circuit and the second latch circuit is configured by an SRAM (Static Random Access Memory) type.

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International Search Report issued in International Patent Application No. PCT/JP2008/002560, dated Oct. 14, 2008.
Written Opinion of the International Searching Authority issued in International Patent Application No. PCT/JP2008/002560, dated Oct. 14, 2008.

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