Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-18
2001-02-27
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S335000, C257S345000, C438S156000, C438S163000, C438S194000, C438S212000, C438S300000
Reexamination Certificate
active
06194760
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a fabricating method thereof, and in particular, to a double-diffused metal oxide semiconductor (DMOS) transistor and a fabricating method thereof, which can reduce on-resistance (Rds) by decreasing chip size.
2. Description of the Related Art
Semiconductor technology has recently been moving toward integrating power devices such as DMOS transistors, IGFETs (Insulated Gate Field Effect Transistors), and the like on a chip in a high density. These power devices, finding their wide use as individual devices and power ICs (Integrated Circuits), have channels formed by double-diffusion.
In particular, a DMOS transistor, obtained by double-diffusion, has impurity regions of different conductive types formed by sequentially diffusing impurities of different conductive types through a hole in an insulating layer. The double-diffusion structure of the DMOS transistor enables a short channel to be formed with high precision and the DMOS transistor to operate at high speed. DMOS transistors are grouped into vertical DMOS (VDMOS) transistors and lateral DMOS (LDMOS) transistors according to their current paths.
FIG. 1
is a sectional view of a conventional N-channel DMOS transistor. Referring to
FIG. 1
, an N+ buried layer
12
is formed on a P-type semiconductor substrate
10
, and an N-type epitaxial layer
14
is formed over the substrate
10
and the N+ buried layer
12
. A device isolation region
17
is formed over the N-type epitaxial layer
14
, and an N+ sink region
16
is formed under a drain contact forming area by diffusing an N-type impurity of high concentration into the N+ buried layer
12
.
A gate electrode
20
is formed over the N-type epitaxial layer
14
with a gate oxide film
18
formed between the two. A P-type body region
22
is formed into the surface of the N-type epitaxial layer
14
, and an N+ source region
24
is formed to be surrounded by the P-type body region
22
in self-alignment with the gate electrode
20
. An N+ drain region
26
is formed into the surface of the N-type epitaxial layer
14
in non-self-alignment with the gate electrode
20
from the outside thereof A channel region (not shown) is formed into the surface of the P-type body region
22
partially overlapped with the gate electrode
20
.
An insulating layer
30
having a contact hole is formed over the N-type epitaxial layer
14
including the gate electrode
20
. A metal layer
32
is formed in the contact hole of the insulating layer
30
to make contact with the gate electrode
20
, the N+ source and drain regions
24
and
26
, and the P-type body region
22
in the DMOS transistor.
In the conventional DMOS transistor as constituted above, a bulk bias region
28
should be formed to simultaneously make contact between the metal layer
32
and the N+ source region
24
and between the metal layer
32
and the P-type body region
22
. In this way, the entire chip size is increased, in turn, increasing on-resistance.
SUMMARY OF THE INVENTION
To circumvent the above problems, an object of the present invention is to provide a DMOS transistor which can reduce chip size to lower on-resistance (Rds).
Another object of the present invention is to provide a suitable method of fabricating the above DMOS transistor.
To achieve the first object, there is provided a double-diffused MOS transistor. The double-diffused MOS transistor includes a semiconductor substrate, a buried layer of a first conductive type formed on the semiconductor substrate, an epitaxial layer of the first conductive type formed over the semiconductor substrate and the buried layer, a gate insulating film formed over the epitaxial layer, a gate electrode formed over the gate insulating film, a source region of the first conductive type formed in the surface of the epitaxial layer in self-alignment with the gate electrode, a drain region of the first conductive type formed in the surface of the epitaxial layer in non-self-alignment with the gate electrode, a body region of a second conductive type formed in the surface of the epitaxial layer and surrounding the source region, and a bulk bias region of the second conductive type formed below the source region at a greater depth than the source region.
Preferably, a sink region of the first conductive type is formed from under the drain region to the buried layer to reduce drain resistance.
In addition, an insulating layer may be formed on the epitaxial layer including the gate electrode, and a metal layer may be formed on the insulating layer, for making contact with the gate electrode, the source and drain regions of the first conductive type, and the bulk bias region.
To achieve the second object of the present invention, there is provided a double-diffused MOS transistor fabricating method. The double-diffused MOS transistor fabricating method includes the steps of sequentially forming a buried layer of a first conductive type and an epitaxial layer of the first conductive type over a semiconductor substrate, forming a gate insulating film over the epitaxial layer, forming a gate electrode over the gate insulating film, forming a body region of a second conductive type in the surface of the epitaxial layer by ion-implanting an impurity of the second conductive type using a photomask, forming a source region of the first conductive type into the surface of the epitaxial layer by ion-implanting an impurity of the first conductive type into the surface of the resultant structure, forming a drain region of the first conductive type into the surface of the epitaxial layer by ion-implanting an impurity of the first conductive type into the surface of the resultant structure, and forming a bulk bias region of the second conductive type below the source region by ion-implanting an impurity of the second conductive type into an area having a width smaller than that of the source region using a photomask.
A sink region of the first conductive type may be formed by ion-implanting an impurity of the first conductive type into a drain forming area and diffusing the ion-implanted impurity to the buried layer. This step is performed after the step of sequentially forming the buried layer of the first conductive type and the epitaxial layer of the first conductive type, and serves to reduce drain resistance.
Preferably, no photomask is used in the step of forming the source and drain regions of the first conductive type.
After the step of forming the bulk bias region of the second conductive type, an insulating layer is formed on the surface of the resultant structure, the insulating layer is etched over the area having a width smaller than that of the source region of the first conductive type, the exposed epitaxial layer is etched to the body region, the insulating layer on the drain region and the gate electrode is etched, and a metal layer is formed on the surface of the resultant structure.
To achieve the second object of the present invention, there is provided a double-diffused MOS transistor. The double-diffused MOS transistor includes an epitaxial layer of a first conductive type, a gate electrode formed over the epitaxial layer, a source region of the first conductive type formed in the surface of the epitaxial layer, a drain region of the first conductive type formed in the surface of the epitaxial layer, a body region of a second conductive type formed in the surface of the epitaxial layer and surrounding the source region, and a bulk bias region of the second conductive type formed in the body region of the second conductive type at a depth greater than the source region.
In addition, a sink region of the first conductive type is formed from under the drain region to reduce drain resistance. Also, an insulating layer may be formed over the epitaxial layer and the gate electrode. A metal layer may also be formed over the epitaxial layer, for making contact with the gate electrode, the source and drain regions, and the bulk
Jones Volentine, L.L.C.
Samsung Electronics Co,. Ltd.
Wojciechowicz Edward
LandOfFree
Double-diffused MOS transistor and method of fabricating the... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Double-diffused MOS transistor and method of fabricating the..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double-diffused MOS transistor and method of fabricating the... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2597617