Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-28
2004-03-30
Lee, Eddie (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S306000, C438S307000, C438S369000, C438S372000, C438S519000, C438S546000, C438S547000, C438S529000
Reexamination Certificate
active
06713351
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor wafer processing and more particularly to a method for forming a double diffused field effect transistor.
BACKGROUND INFORMATION
Power MOSFET devices are well known and are used in many applications including automotive electronics, portable electronics, power supplies, and telecommunications. One important electrical characteristic of a power MOSFET device is its on-state resistance (R
DSon
), which is defined as the total resistance encountered by the carriers as they flow from the source terminal to the drain terminal. In order to allow manufacturers to produce power MOSFET devices having higher current carrying capability in smaller packages, it would be advantageous to have MOSFET structures that reduce the on-state resistance
FIG. 1
is a simplified cross-sectional diagram of a conventional n-channel power MOSFET referred to as a double diffused field effect transistor. A layer of N type epitaxial silicon
1
is formed on an N+ type substrate
2
. A P body region
3
A and a P+ body region
3
B are formed into the epitaxial layer from upper surface
4
, and an N+ type source region
5
is formed into the body regions
3
A and
3
B from upper surface
4
. To turn the transistor on (i.e., make it conductive), a positive potential is placed on gate
6
. The positive potential on gate
6
causes what is called a channel region to form in the surface portion of P body region
3
A underneath the gate and also causes what is called an accumulation region to form in the surface portion of the N type epitaxial silicon region
1
A immediately underneath the gate. Electrons can then flow as generally indicated by the arrow from the N+ type source region
5
, through the channel region in P body region
3
A, through the accumulation region of N type epitaxial layer
1
A, downward through the N type epitaxial region
1
A, downward through the N+ type substrate
2
, and to a drain electrode
7
. If gate
6
does not have a positive potential, then no channel is formed and no electron flow from source to drain takes place. The transistor is therefore turned off (i.e., nonconductive).
FIG. 2
is a simplified cross-sectional diagram of another type of double diffused field effect transistor, a trench field effect transistor. In
FIGS. 1 and 2
like elements are represented by reference numerals. An N type epitaxial layer
1
is formed on a N+ type substrate
2
. Body regions
3
A and
3
B and N+ type source region
5
are then formed in similar double diffused fashion to the body and source regions in the planar transistor. In the case of the trench transistor, a trench is etched down into epitaxial layer
1
from upper surface
4
. A gate oxide layer
8
is then grown in this trench on the side walls and the trench bottom. An amount of polysilicon or other suitable material is then deposited on the gate oxide in the trench to form a gate
9
. For additional information on trench field effect transistors, see U.S. Pat. No. 5,072,266 entitled “Trench DMOS Power Transistor With Field-Shaping Body Profile And Three-Dimensional Geometry”, the subject matter of which is incorporated herein by reference.
To turn the trench transistor on, a positive potential is placed on gate
9
. The positive potential causes a channel region to form in the portion of the P body region
3
A which forms part of the sidewall of the trench and causes an accumulation region to form in the portion of the N type epitaxial layer region
1
A which forms a part of the sidewall of the trench. Electrons can then flow as indicated by the arrow from the N+ type source region
5
, downward through the channel region of P body region
3
A, downward through the accumulation region, downward through the remainder of the N type epitaxial region
1
A, downward through the N+ type substrate
2
, and to a drain electrode
7
. If gate
9
does not have a positive potential, then no channel is formed and no electron flow from source to drain takes place. The transistor is therefore turned off.
It is desirable that such transistors have low source-to-drain resistances R
DSon
when turned on. As depicted pictorially in
FIG. 1
, the resistance R
DSon
in the planar structure is made up of the resistance R
CH
through the channel, the resistance R
ACC
laterally through the accumulation region, the resistance R
JFET
vertically through the pinched portion of the N type epitaxial region
1
A between the two adjacent P body regions, the resistance R
DRIFT
vertically through the remainder of the N type epitaxial region
1
A to the substrate, and the resistance R
SUB
vertically through the substrate to the drain electrode. As depicted pictorially in
FIG. 2
, the resistance R
DSon
in the trench structure is made up of the resistance R
CH
vertically through the channel, the resistance R
ACC
vertically through the accumulation region, the resistance R
DRIFT
vertically through the remainder of the N type epitaxial region
1
A, and the resistance R
SUB
vertically through the substrate to the drain electrode. Note that R
JFET
is eliminated in the trench device. Because the conductivity of silicon increases with dopant concentration, epitaxial silicon layer
1
is relatively heavily doped to reduce the R
DRIFT
and thereby reduce R
DSon
.
It is also desirable that such transistors have a high breakdown voltage so that they can be operated at high voltages and thus serve as high power devices. As is well known to those or ordinary skill, the breakdown voltage increases with decreasing dopant concentration in the epitaxial region
1
A and increasing thickness of the epitaxial region
1
A. Since the magnitude of the on-resistance and the breakdown voltage vary in a similar manner with respect to dopant concentration, decreasing the on-resistance of a double diffused field effect transistor by increasing the doping concentration in the epitaxial region
1
A causes an undesirable decrease in the breakdown voltage of the device.
U.S. Pat. No. 6,084,268 discloses a power MOSFET in which the on-resistance is reduced by providing regions of localized doping within the epitaxial layer
1
A. The regions of localized doping have the same conductivity type as epitaxial layer
1
A, but with a higher dopant concentration, thereby lowering the series resistance between the channel regions and the drain region of device. Also, the regions of localized doping are limited so that they are spaced apart from p-type regions
3
B to minimize a decrease in breakdown voltage that may also arise. On problem with this technique is that it requires additional masking steps and high energy ion implantation techniques to form the localized doping region.
Accordingly, it would be desirable to provide a double diffused field effect transistor having a reduced on-resistance without detrimentally impacting the breakdown voltage of the device and which is also relatively easy to manufacture.
SUMMARY OF THE INVENTION
The present invention provides a double diffused field effect transistor and a method of forming the same. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.
In accordance with one aspect of the invention, the gate region is formed by locating a plurality of trenches within the epitaxial layer and then lining the trenches with a first insulating layer. A polysilicon conductor is provided within the trenches and overlies the first insulating layer.
In accordance with yet another aspect of the invention the d
General Semiconductor Inc.
Lee Eddie
Magee Thomas
Mayer Fortkort & Williams PC
Mayer, Esq. Stuart H.
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