Double data rate output latch for static RAM device has...

Details Double data rate output latch for static RAM device has... Double data rate output latch for static RAM device has...

2009-08-19

2011-11-29

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C327S153000, C365S233130

Reexamination Certificate

active

08069363

ABSTRACT:
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second transparent latch receives data from the first transparent latch and outputs data dependent on a delayed output clock which is the output clock delayed by an insertion delay. An output latch receives data from the second transparent latch and synchronizes data to the output clock.

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